PROGRAMMER

TM 11-5820-918-13

4-55. PROGRAMMER (figure FO-32) (S/N 400100 and before). A 5 MHz input from

the synthesizer is gated into U6 and continues through a fixed divider chain ending

in U29. The resultant frequencies are 100 kHz at TP2 and 1 Hz at TP1. A BCD down

counter to drive the front panel digital clock is formed by U30 (1 second), U24 (10

seconds), U22 (1 minute), and U28 (10 minutes). A BCD group branching off the

same down counter into U16 and U10 is used to decode five minute segments from the

front panel switch scanner circuit formed by U26 and U20. Every five minutes the

next programmer switch on the front panel is interrogated by this scanner. If a switch

is closed (ON), a pulse is passed through the programmer switch contacts and into

the PSC (Common) terminal which then clocks U14. U14 triggers a one-shot (U21)

which sends an auto-start pulse back to the synthesizer at terminal AST. At the end

of each sweep, U14 is cleared to reset the auto- start circuit and await another PSC

pulse from the front panel switches. U1 and U2 form part of the network which inter-

faces the front panel switches with the internal logic. These are switch debounce

flip flops to prevent spurious transients from being gated as pulses. U13, U3, and

U9 form a decoder that determines which switches are enabled based on the position

of the MODE switch. In the manual (MAN) mode position, the front panel switches

for sweep START, STOP, and RESET are enabled. In the SET mode position, START

and RESET are enabled. In the continuous and program modes, the three switches

are disabled. Transistors Q1 through Q6 are lamp drivers to indicate which of the

front panel switches are enabled. Two one- shots formed by U8 have pulsed outputs

which are enabled when the advance timer or reset switches are actuated. Their func-

tion is to either advance the minutes decades or reset the digital clock.

4-56. TEST CIRCUIT (figure FO-32) (S/N 400100 and before). The test circuit pro-

vides a go/no-go check of all DC power supplies, the battery supply, and synthesizer

phase locked loop. The test is made by pressing the front panel TEST pushbutton

and interpreting the indicators mounted adjacent to the switch. The method of ANDing

the inputs to indicate test status is shown on the schematic ( FO-23). All the low volt-

age DC inputs are monitored, The +29 volt input comes from the switching regulator

and effectively checks the +35 VDC unregulated supply. The input OOL (out of lock]

comes from the synthesizer and is low if the phase locked loop is not locked. The

LT input is not used on the transmitter. The output at U38-6 is low when all inputs

are active. With U38-6 low and the test switch depressed, Q8 will conduct (+5 volts),

and the system test green indicator will light. Under the same conditions with U38-

6 high (one or more inputs inactive), Q7 will conduct, turning on the red lamp. De-

tection of battery condition by the front panel test lamps is indicated on the schematic,

(figure FO-32). The test switch serves to enable transistors Q9 and Q10 which drive

the battery indicator lamps. With the test switch actuated, the +5 VB enables U37

and also turns on Q12 which drives Q11 to saturation. The battery voltage is then

sensed by the divider R46, R47, and R48. If the battery voltage is 22 volts or more,

the divider biases Q10 on which supplies 5 volts to turn on the battery green indicator.

If the battery voltage is between 17 and 22 volts, the divider ( R46, R47, and R48)

biases both Q9 and Q10 on which causes both red and green lamps to light. For bat-

tery voltages between 17 and 14 volts, Q9 is biased on the red lamp lights. Voltage

below 14 volts is not sufficient to turn on either transistor and both indicator lamps

remain off.