NUMERIC DISPLAY AND DRIVER

TM 11-5820-918-13

into U24, U32, U40, and U48, the outputs of which are delivered to U8, U14 through

U16 and on to the LED display (frequency section). Basic timing for the counter is

derived from a 100 kHz clock which is divided by U1 and U3 to 1 kHz. This 1 kHz

is divided down to 125 Hz at U9-5. U10 and U33 form a circuit which makes the 125

Hz, 4 ms gate waveform slightly asymmetrical to avoid counter indecision when the

synthesizer is stopped at exactly 2 MHz (when reset). One-shot U18 generates a nom-

inal 10 microsecond latch/load pulse that strobes the new BCD frequency into the

latches following the count period.

4-30. Frequency Blanker (figure FO-15) (S/N 400101 and on). The frequency blanker

section provides storage and control for 16 discrete frequencies about which the RF

output of the TCS-4B is gated off for 30 kHz of sweep width. U11, U19, U35, and

U43 are 64-bit (16 x 4) random access memories which store the desired blank fre-

quencies. The frequency and channel (1 of 16) are entered by front panel thumb-

wheel switches. The RUN/PROG switch must be in the PROG position to enter fre-

quencies. Entry is then made by pressing the STORE pushbutton switch. The con-

tents of each channel are examined by pressing DISPLAY (only in PROG position)

and observing the frequency readout of the LED display. Placing the RUN/PROG

switch to the RUN position causes U4 to count instead of load and thereby cycles

through all address codes of the memories every 4 milliseconds. The memories re-

ceive the frequency data in true BCD form and invert the data on their outputs.

The output data must then be inverted to have "true" data again. The memories are

primary power failure, preserving the contents of the memories.

4-31. The data from the memories is presented to a four decade comparator, com-

prising U21, U29, U37, and U45, U22, U30, U38, and U46 forms a counter identical

with U23, U31, U39, and U47 except U22 is loaded with a preset count. This preset

count number causes the compare pulse on U45-6 to be 30 kHz ahead of the true count

frequency. This pulse then sets U34-5 high which starts the blanking process. U25

then shifts (6 shift pulses) this pulse down to pin 11 which terminates the blanking.

The shift clock is generated by the synthesizer and is always equal to 10 kHz of sweep

bandwidth regardless of sweep speed.

4-32. NUMERIC DISPLAY AND DRIVER (figure FO-16 and FO-17). The numeric dis-

play (figure FO-16) consists of two blocks of four digits. The first block (LED 1 thru

4) displays elapsed program time in minutes and seconds and has a fixed colon (CR1

and CR2) separating the minutes from the seconds. The second block (LED 5 thru

8) displays frequency in megahertz to two decimal places. The decimal point is per-

manent and is placed at the start of the third digit (activated by R65 to ground). The

path digit (LED 9) is not used on the transmitter.

4-33. The LED display is driven by eight BCD to 7-segment decoder drivers (figure

FO-17). The drivers accept positive true BCD time and frequency information from

the 5-minute timer and frequency counter and translate the information to 7-segment

negative true outputs for the common anode LED readouts.

4-34. PRIMARY POWER SUPPLY (figure FO-18). The primary power supply provides

all the DC voltages used in the transmit sweep generator unit. Voltages provided

are +12 VDC, -12 VDC, +24 VDC, +35 VDC, and multiple +5 VDC outputs, both reg-

ulated and unregulated. The three regulated +5 VDC outputs supply the logic vol-

tage for both the synthesizer and the programmer circuits. The single +5 VDC unreg-

ulated output provides power for front panel indicators including the LED display.

The +5 VDC regulated supplies are separated to isolate noise signals between circuits.

The +12 VDC, -12 VDC supplies and the +24 VDC supply (all regulated) are used for

4-12