DOWN CONVERTER - TM-11-5820-918-130056

TM 11-5820-918-13

basis every 10s. All timing signals needed by the synthesizer are produced by the

timing generator circuit. The timing generator controls the timing of the transfer

of frequency data input to the phase register and divide-by-N counter, and controls

the timing of the fractional phase correction (residue) circuitry.

4-24. DOWN CONVERTER (figures FO-9 and FO-10). The 5035-2002 down converter

circuit 1A1A2 generates additional synthesized signals derived from the 5 MHz fre-

quency standard and the 40-70 MHz synthesizer output which are required for trans-

mitter (or receiver) use. The primary function is to translate the 42-70 output of

the synthesizer to a 2-30 MHz output for the transmit sweep. The 5 MHz input from

the frequency standard is buffered by the down converter circuit and frequency

multiplied to 40 MHz by the harmonic generator and 40 MHz bandpass filter. The 40

MHz is then mixed with an amplified 40-70 MHz signal from the synthesizer. The out-

put produce of the mixer is the 2-30 MHz transmit sweep which is further amplified

and filtered to produce a 0 dBm (one milliwatt) sine wave output. The down converter

also features a gating circuit which turns off the 2-30 MHz output when it is not need-

ed. Gating is used for blanking of the TCS-4B transmit sweep at selected frequencies.

4-25. SWEEP PROGRAMMER (figures FO-11 and FO-12). The 5035-2003 sweep pro-

grammer circuit 1A1A3 controls the frequency sweep by digitally programming the

synthesizer to advance its output frequency in 1 Hz steps every 10 microseconds.

The sweep programmer contains an 8 decade BCD counter that stores the programmed

frequency data of the synthesizer. This is preset with the sweep starting frequency

(low limit) of 2 MHz. When the sweep START command (from the sounder control

logic) is received, a 100 kHz clock from the synthesizer is gated on to the 8 decade

counter. The counter increments by one count on every pulse of the 100 kHz clock.

This advances the preset count by one Hz every 10 s resulting in a linear increase

in the programmed frequency corresponding to a 100 kHz per second sweep rate. The

sweep continues until it reaches 30 MHz when the upper limit detect circuit interrupts

the 100 kHz clock thereby stopping the sweep and resetting the 8 decade counter

back to the 2 MHz low limit. If a 2-16 sweep is selected the sweep programmer oper-

ates as described above except the upper limit detector is set to 16 MHz and the

sweep clock is divided by 2 to 50 kHz.

a. The sweep programmer also contains slip circuits and clock gating circuits which

increase or decrease by basic 100 kHz (or 50 kHz) sweep clock by 0.1, 1.0, or 5.0%.

The resulting sligght changes in sweep rate allows the RCS-4B receiver sweep to be

advanced or retarded relative to the TCS-4B transmit sweep for synchronization pur-

poses. This slip circuitry is not used in TCS-4B applications. The blank control

circuit drives RF gating circuits in the synthesizer down converter and the TCS-4B

transmitter RF power amplifier output low pass filter set. When a blanking pulse is

generated by the frequency counter/blanker (1A2A2), the sweep programmer blank

control circuit determines the length of the blank interval. Earlier versions of the

TCS-4B transmitter used a 20 kHz wide (10 kHz) blanking interval while newer ver-

sions employ a 60 kHz interval.

b. The sweep programmer also contains two digital dividers; the 100 kHz reference

generator, and the VCO divide-by-20 counter. The input to the 100 kHz reference

generator is the 5 MHz standard which is digitally divided by 50 to produce 50 nan0-

second wide pulses a 100 kHz rate. These pulses drive the synthesizer phase detector

reference input. The VCO divide-by-20 counter takes the 42-70 MHz synthesizer out-

put and divides it to the 2.1- 3.5 MHz count output for use by the frequency counter

logic that, in turn, drives the LED displays.

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