AUTO START

TM 11-5820-917-13

is set. Pushing the CURSOR FREQ pushbutton switch (CFS) routes the BCD

cursor information (CCK) to the LED display.

4-98. The logic for the cursor to frequency conversion is represented in the

block diagram of figure 4-4 and this function is performed bv the circuits on the

cursor storage and readout (1A2A1) and receiver control (1A4A2). Every ten

milliseconds the start/stop flip-flops U9 gate the 400 - 700 kHz clock (the exact

rate is arbitrary) into the up-and down-counters, a borrow (end-of-count) pulse

is issued which stops the clock. Since the count rate for the BCD up-counter

was the same as for the binary down-counter, the total count added to the pre-

load of 0199 provides the BCD equivalent of cursor frequency in megahertz. At

the end of ten milliseconds, the two counters are cleared, the load enable activated,

and the count process repeated. Assuming the moving cursor to be stationary,

the frequency of the moving cursor appears at the outputs of BCD up-counters

U25-28 every ten milliseconds and remains latched at U1-U4 (figure FO-38/3) for

the same period. Hence, actuation of the CURSOR FREQ switch throws the 16-

pole switch (U17-20) between the BCD counters and the LED display via the

latches, making a current cursor readout available at a refresh rate of two milli-

seconds.

4-99. AUTO START (figure FO-38/4). The purpose of the auto start circuit is to

receive start time information for the PATH PROGRAMMER switches, start the

synthesizer, and start loading the appropriate CRT memory. Each pair of flip-

flops (U45, U53, or U61) are for a single path. The two inputs necessary to

trigger the CRT memory load function (TVL1) are: 1) a pulse through the (PS1)

path programmer #1 bus (signifying any #1 PATH PROGRAMMER switch selected)

and 2) a pulse through 1 CLK input (signifying that a new 5-minute interval is

starting) from the path programmer circuit (paragraph 4-91). The two hex

inverters (U52) provide a slight time delay so the second half of the flip-flop re-

sets (gets armed) before active toggling on the new pulse. Each of the path flip-

flops operate in the same way; however, a gating circuit (U44) prevents active

switching of the other two paths once a legitimate output is detected. The active

TVL line is routed to the memory load logic for display and memory load. Simul-

taneously, the synthesizer is enabled (AST - for any path) for sweep start.

After the sweep is completed, a return pulse from the synthesizer (EOS) clears

the output flip-flops ready for the new selection.