3-PATH CONTROLLER 1A4 ( S/N 400100 and before)

TM 11-5820-917-13

4-88. The switching regulator circuit 1A6A3 (figure FO-36) regulates the +5-volt

power input to the primary timing circuits of the receiver. The circuit is basi-

cally intended for regulation of the battery supply during a power failure. How-

ever, in normal operation, a line power derived source of 29 VDC (from CR4+)

is routed through the same circuit allowing unbroken interruption of power should

a supply failure occur. The high efficiency (65%) circuit contained on this board

uses a low current drain voltage regulator connected as an oscillator (U1) in which

an inductor (L2) is used in the feedback loop as an energy storage device. By

controlling oscillation, the inductor effects" internal conduction of the regulator/

oscillator, thereby cent rolling volt age. A 1.6A current limiter (Q4, Q5, and Q6)

and a 6 volt, 5 watt, overvoltage protector, (CR6 and CR10) are included as an

integral part of the circuit. A related circuit senses the input line to determine

if the battery voltage is less than 16.3 volts. This is achieved at U2 by comparing

the received voltage to two zener diodes, the difference voltage thereby controlling

Q7, which in turn controls turn-on of oscillator U1.

3-PATH CONTROLLER 1A4 ( S/N 400100 and before)

4-90. 3-PATH PROGRAMMER 1A4A1 (figure FO-37). The 3-path programmer

circuit performs three basic functions: it provides precision five minute timing,

using a count down of the 5 MHz frequency standard; it generates advance and

retard pulses to slip each path in time to synchronize it with the related trans-

mitter; and it provides a LED display decode for either path 1 or any other switch-

selected path time.

4-91. The incoming 5 MHz is initially divided down to 100 kHz by U17 and U10

(figure FO-37/1) and routed to the three separate path timer inputs (MCK). Each

path timer then divides the 100 kHz down, first to one pulse per second for exter-

nal sampling, and then into seconds and minutes for the LED display logic switch.

The LED display logic switch is a 16-pole, 3-throw logic circuit switched elec-

tronically by three SET positions of the MODE select switch. When the MODE

select switch is not in a SET position, path 1 is automatically selected since only

one path time can be displayed. The selected path is routed directly to the LED

display driver circuit for display of the time segments. In addition to the basic

five-minute count, each path timer sends a sequential five-minute pulse to each

of the PATH PROGRAMMER switches (0-MINUTE position, 5-MINUTE position,

10-MINUTE position, etc.), The pulse is negative-going for one millisecond.

If the switch for that path is active at any of these times, it is routed to the auto

start circuit for activation of the CRT memory and synthesizer start functions.

4-92. The slip generator (figure FO-37/1) uses a timing and gating technique to

add or delete pulses from the 100 kHz input frequency of any path. A pulse train,

whose frequency is selected by the front panel SLIP RATE MS /SEC switch, is

gated to the two one-shots, U18. The positive (MSP), or advance, output pro-

duces narrow pulses which are added into the 100 kHz stream to slip the path

position forward in time. The negative (MSN), or retard, output develops a nega-

tive- going pulse of identical duration and position (i.e. in sync) as the 100 kHz

stream which, when gated into the select paths input, effectively cancels existing

synchronous pulses, thereby retarding the clock time.