DOWN CONVERTER - TM-11-5820-917-130091

TM 11-5820-917-13

Because the synthesizer basic timing reference is 100 kHz, the divide-by-N

The phase detector and loop amplifier will then try

and 436 cycles for one frame.

The resulting VCO output is a phase modulated signal with an average center fre-

quency of 43.501 MHz with 1 kHz sidebands. The 1 kHz sidebands result from the

such that the VCO remains steady at the average frequency and does not follow the

loop back and forth between the two programmed frequencies. However, to reduce

the sidebands to an acceptable level (-50dBc) would require smoothing (slowing)

the loop response to such an extent that the synthesizer would no longer be suit-

able for sweeps used in Chirp sounder applications. These sidebands may be can-

celled however, using a fast loop and a fractional phase correction circuit operating

in conjunction with the divide-by-N.

c. Since the average frequency of the VCO is correct, the average value (or

DC component) of the VCO control voltage from the loop amplifier is correct. The

undesired 1 kHz sidebands are produced by the sudden phase errors generated

when the divide-by-N counter jumps between the two programmed integer divide

numbers. This produces a small momentary change in the VCO control voltage

which modulates the VCO frequency resulting in sidebands. The fractional phase

correction circuit cancels the VCO modulation by injecting a compensating phase

error correction signal into the loop amplifier to counteract the effect of the phase

error jump when the divide-by-N skips from one divide ratio to another. The phase

next and simultaneously programs the residue logic of the fractional phase correc-

tion circuits. The residue logic, in turn, drives the residue generator, which pro-

duces the residue fractional phase error correction signal. By careful alignment of

the residue generator the synthesizer sidebands can be suppressed better than 50

dB below the fundamental output level. The divide-by-N counter consists of a VCO

prescaler which typically divides the VCO output frequency by 2. The prescaler

also contains a pulse skipper circuit that makes the divide-by-2 circuit skip one

extra VCO clock pulse each time a skip command is given. This effectively turns

VCO prescaler drives the VCO divider. The combination of the VCO divider and the

VCO prescaler is capable of dividing by any integer number between 400 and 700.

For example, to divide by 437, the VCO counter down counts 430 times and the

VCO prescaler skips 7 extra VCO clocks during the count sequence, yielding a

total count of 437. The phase register accepts binary-coded-decimal (BCD) fre-

quency program data from the sweep programmer card. All 7 decades of BCD data

nals needed by the synthesizer are produced by the timing generator circuit. The

timing generator controls the timing of the transfer of frequency data input to the

phase register and divide-by-N counter, and controls the timing of the fractional

phase correction (residue) circuitry.

4-73. DOWN CONVERTER (figure FO-27). The 5035-2002 down converter circuit

2A1A2 generates additional synthesized signals derived from the 5 MHz frequency

standard and the 40-70 MHz synthesizer output which are required for receiver (or