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TM 11-5820-917-13
NOTE
The synthesizer module is used interchangeably in both transmit (TCS-4B)
and receive (RCS-4B) applications.  A programming line in the instrument
wire harness determines whether the synthesizer operates in the transmit
or the receive mode.
The sweep synthesizer module has five RF outputs:  (1) the 42-70 MHz first mixer
L.O. injection for the receiver;  (2) the 40 MHz second L.O. receiver injection;
(3) a buffered 5 MHz from which the receiver third mixer L.O. injection is derived;
(4) the 2.1- 3.5 MHz count output which is used by the frequency counter in the
TCS-4B transmit logic, or RCS-4B receiver control logic to drive the front panel
LED frequency display; and (5) the 2-30 MHz transmit sweep output which drives
the TCS-4B RF power amplifier or the RCS-4B receiver calibrator circuits. The
one RF input to the sweep synthesizer is the 5 MHz frequency standard signal
from which all RF outputs are derived.  The synthesizer digital inputs select
parameters such as:  sweep rate and limits; sweep start, stop and reset; RF blank-
ing; slip; auto sync and RF output power level.  The module consists of three cir-
cuit card assemblies:  synthesizer 2A1A1, down converter 2A1A2, and sweep
programmer 2A1A3.
4-72. SYNTHESIZER (figures FO-25 and FO-26).  The 5035-2001 synthesizer cir-
cuit (2A1A1) is a digitally programmed, phase-locked-loop synthesizer capable of
generating any frequency between 42 and 70 MHz to 1 Hz resolution. It consists
of a 42-70 MHz VCO, a programmable divider (divide-by-N), a phase detector and
loop amplifier, and control logic (phase register and timing generator). Figure
4-11 is a simplified diagram of the circuit.  A detailed functional block diagram is
a.  The output frequency of the VCO (and the synthesizer) is determined by
electrically tuning the VCO with a control voltage from the loop amplifier.  The loop
amplifier produces this control voltage by integrating (smoothing) the phase-error
signals generated by the phase detector.  If there is no phase error, the output of
the phase detector is zero and the loop amplifier will hold the VCO at its existing
frequency.  If there is a phase error the phase detector will drive the loop ampli-
fier to change the VCO frequency until the error is corrected. The synthesizer
uses the phase detector to compare the output of the divide-by-N counter with a
fixed 100 kHz reference signal.  If the phase or frequencies of these two signals
do not match, the phase detector will drive the loop amplifier to adjust the VCO
frequency until the divide-by-N output exactly matches the 100 kHz reference,
thereby achieving phase lock.  The VCO output frequency is always N times 100
kHz.  There are N cycles of the VCO output for every one cycle of the 100 kHz
reference.  If N is an integer number, the VCO frequency will be an exact multi-
ple of 100 kHz.  However, if N is a number consisting of both integer and fraction-
al components, intermediate frequencies between 100 kHz points may be synthe-
sized.  For example, to produce a 43.5 MHz output the divide-by-N counter must
divide by 435.  If an output of 43.501 MHz is desired, the required divide ratio is
435.01. The divide-by-N counter, however , is a 3 decade counter only capable of
dividing by integer numbers between 400 and 700.  To divide by 435.01 the phase
register circuitry programs the divide-by-N to divide by 435 for 99% of the time
and divide by 436 for the remaining 1%.  The resulting average divide number is
(99+ 435) + (1 + 436)= 435.01
.
100


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