CRT DISPLAY MEMORY ( 1A3A1)

TM 11-5820-917-13

period, one memory is read in and presented for half of the clock period, and

then the other memory is read for the other half of the clock period, producing

an effective 2.4 MHz bit rate at U 47-12 to be presented to the memory video

circuit.

4-50. Frequency marks are generated for every 20 vertical TV lines which is

equivalent to each MHz in the 2-16 MHz format or each 2 MHz in the 2-30 MHz

format. A counter formed by U 5 and U 11 (figure FO- 16/4) divides by 20 the

vertical sync pulses ( VS 1) , which occur for every vertical line, enabling a fre-

quency mark flip-flop U20 to be set every 20 lines. The frequency mark infor-

mation is available for the full vertical scan at U 20-6. This in turn is gated

into the video of the CRT at U17- 11. At the start of each CRT raster line, a 2-

microsecond gate signal provided at U 9-7 enables the lower frequency mark to

appear on the screen. A second one- shot output on U 9-10 enables the frequency

marks to appear at the top of the screen after 63 microseconds of vertical scan

time. The frequency mark data causes U15- 8 to go high, resulting in a white

output on the screen. The screen could also be white as a result of noise or

AGC data thus obliterating the frequency marks. However, U 15 and U 16 comprise

an exclusive-or circuit to ensure that the frequency marks appear as white-on-

black or black-on-white depending on the other signal inputs to the CRT video

combiner (U15 and U16) . Characters appear at the bottom of the CRT display

as a result of any input to U17- 10 on line PNG from assembly 1A2A2. All cur-

sors, moving, fixed, or load, are combined at, and then gated to, the CRT by

U 17-3. The video information from the CRT memory comes from line MVO which

contains the combined circulating CRT memory data. This data is gated onto

the screen from U 17-6.

4-51. CRT DISPLAY MEMORY ( 1A3A1) . This circuit contains three, 36k-bit

memories consisting of 36, 1024-bit MOS shift registers each and associated

clock drivers. The complete circuit is repeated three times, one for each path.

NOTE

The circuit for only one path is shown in the schematic diagram, figure

FO-17.

The memory for each path is divided into two banks of 18 x 1024 bits. Both

banks are loaded at the same time. The data enters at odd and even inputs

MI 1 and MI 2, respectively, and is clocked into the memory by

at 1.2 MHz.

three banks of memory, each containing one complete CRT path display, con-

tinually circulate via the gating logic from the memory load logic circuit (1A 3A2) .

When new data comes in, it is gated in place of that path's circulating memory.

Therefore, as long as primary power to the receiver remains on, the most

recently received path data is always available for display. (The standby battery

supply does not refresh the memory in the event of primary line failure. ) The

2-phase memory clock is buffered by transistor clock drivers to provide an

approximate +10 to -6 volt clock swing required by the MOS shift register

memory.