MEMORY LOAD LOGIC ( 1A3A2) (cont)

TM 11-5820-917-13

Much of the logic activity is established during the vertical retrace interval. The

vertical retrace interval takes 16 clock pulses. The three most significant bits

of counter U42 in assembly 1A2A2 (FO-15/1) are fed to Ul (figure FO-16/4) on

lines CSB1, CSC1, and CSD1.

U 1 is used as a one-out-of-eight decoder which provides individual pulse outputs

in synchronism with the one-out-of-eight multiplexer switch ( U 12-U 20) in assem-

bly 1A2A1. If new spectrum data is to be loaded into the memory, an EQT pulse

is generated by timing and control circuit 1A 2A 2 indicating when the raster line

(and therefore, the memory) has arrived at the address location corresponding

to the new data to be loaded. The EQT pulse is applied to latch U 3-2. When U 1

reaches " 7", the output on U 1-9 goes low enabling a strobe pulse coming from

U8-9 to clock U3. The strobe occurs in the middle of the EQT pulse. The out-

put on U3-5 is fed via U12-6 and U14-12 to a cursor gate at U17-1 to draw the

load line on the CRT. The output on U 3-5 also becomes the spectrum analyzer

load control line, SAL. The SAL signal remains high for the one CRT vertical

line having the same address number as the spectrum analyzer load line register.

This is used to synchronize the loading of the data from the buffer memory into

the high speed circulating memory.

4-48. The dual 64-bit memory buffers (figure FO- 16/2) consisting of eight,

16-bit shift registers, U 26 through U 33, are loaded at a slow clock rate con-

trolled by the spectrum analyzer sync gate, SLB. When this signal is high,

meaning that a spectrum analyzer scan is in progress, alternate odd and even

clocks are gated into the clock lines of each of the corresponding odd or even

memory buffers by switch U 25. The data from the spectrum analyzer and the

AGC data from the HF receiver are presented on the serial data line SSD to both

64-bit shift register buffers. The clocks appear alternately on U 26 through U 29

and U30 through U33. After 128 pulses (or 64 alternate pulses to each group)

are completed, the SLB line falls clocking the outputs of U21- 5 high and U21- 6

low . The next time that the SAL signal goes high, indicating the CRT vertical

raster line equals the spectrum analyzer load line, U22 is clocked and U22- 9

goes high. This causes the load /recirculate gates ( figure FO- 16/3) to switch

the main memory from the recirculate mode to the load mode. (For example,

U44- 11 and U51- 6 are disabled, while U40- 6 and U 49-6 are enabled. ) Note that

there are three memory pairs (odd and even): path 1, Ml and M2; path 2, M3

and M4; and path 3, M5 and M6. (This description follows only path 1 for simpli-

city. ) At the same time, U24- 11 applies 1.2 MHz

clock pulses to the eight

memory buffers to shift their contents out into the circulating memory (via U 40-4

and U49-4) . At the conclusion of the load period, the SAL signal falls clocking

U21- 13 which clears U22- 14 shutting off the load sequence and restoring normal

memory recirculation.

and using pins 6 and 3 to control a switch which alternately feeds the outputs of

the odd memory and even memory to the video line for one-half of the normal

1.2 MHz clock. The memories are read out alternately. The rising clock edge

of U43- 11 causes the odd data present at U 43-12 to be transferred to U 47-13.

At the falling edge of the clock, U 43 is cleared at pin 13. As the clock at U 43-3

rises, even data at U 43-2 is transferred to U 47-1 and U 47-2. The falling edge

of the clock at U 43-1 clears this flip-flop. Thus, in 1.2 MHz memory clock

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