CURSOR STORAGE AND READOUT (1A2A1)

TM 11-5820-917-13

pulse of the memory buffers. The second input to the memory, the AGC infor-

mation, is converted into a digital form by a voltage-to-time converter. The

voltage from the AGC is buffered and adjusted in level by U63 from a zero-volt

level with no signal in the receiver to approximately -5 volts with a maximum

interest signal in the receiver. This is fed to comparator U 45. The other input

of U45 starts at zero volts at the end of the 100 clock pulses counted by U 46

and U47 (i.e., the end of the analog spectrum analyzer data period) and ramps

downward to -5 volts in 28 clock pulses. At the time this ramp crosses the

voltage present on U45-3, the output (U45-7) goes low; thus the width of the high

going pulse at TP5 is proportional to'the amplitude of the AGC voltage. The

result on the CRT is a vertical bar proportional in height to the AGC voltage.

4-43. Every other frequency mark on the CRT display is labeled by an elec-

tronically generated character at the bottom of the screen starting with "2" and

ending with either "14" or " 28", depending on the upper frequency limit. These

characters are generated by U21, (figure FO-15/5) which provides a 5 x 7 dot

matrix from standard ASCII code. A parallel-in/serial-out shift register memory,

composed of U12 through U20, stores the successive digits to be displayed

and presents them one after the other to the inputs of the character generator.

Each number displayed on the screen consists of two characters (the numbers

2, 4, 6, and 8 are followed by a blank). Depending on what upper limit has been

selected (16 or 30 MHz), U12-U20 are correspondently loaded with two different

sets of numbers controlled by U7-12 and U27-12. The character generator cir-

cuit is synchronized to the TV raster. The whole shift register buffer train and

counting circuit is started by a pulse (CGS) which comes from the horizontal

synchronizing circuit (U60-10, figure FO-15/2). This pulse occurs at the left

edge of the screen at the beginning of the first line of data. This clears flip- flop

U23-14 and loads the character shift register (U12- U201). At the second frequen-

cy mark occurring after the CGS load pulse, U23 toggles causing the RS latch U26-6

to be enabled. This, in turn, allows a timing pulse (SNG, coming from a vertical

retrace interval counter in assembly 1A3A2) to reach the parallel-in /serial-

out buffer U22 to load it with the data presented by U21. This loading occurs

slightly below the edge of the normal data portion of the CRT vertical trace.

Then, a 2.4 MHz clock (from U44-2) strobes U22 to clock out the 7 bits of the

first line of the first character. The next CRT trace causes the character gen-

erator U21 to output the second vertical line of 7 bits into U22. After the five

vertical lines making up each character are completed plus two blank lines for

spacing, U21-11 goes high triggering the one-shot U24 to shift the nine register

memory one position over presenting the second character to U21. At the end of

this shift, flip-flop U23-5 (via the clock on pin 1) goes high. When the second

character is completed, U23-5 goes low which resets U26-6 and disables SNG pulses

from reaching U22. This condition remains until U23-7 toggles low on every second

frequency mark pulse (FMK).

4-44. CURSOR STORAGE AND READOUT (1A2A1). This circuit assembly

generates a moving vertical line (spectrum analyzer load line) that corresponds

to the current frequency of the receiver sweep. Also, a manually-controlled

moving (blinking) cursor is generated that may be positioned anywhere on the

CRT by the operator. The moving (blinking) cursor may be replaced by a fixed

stored cursor at up to six locations on the CRT. A 9-bit counter (U49-51, figure

FO-14/1), limited to counts of 0-279, generates the address of the next line to

4-22