TIMING AND CONTROL ASSEMBLY 1A2A2 (cont)

TM 11-5820-917-13

4-40. Timing and control circuits (1A2A2) also provide the interface with the

spectrum analyzer used as the signal source for the display. Spectrum analyzer

triggering is controlled by a divider circuit consisting of U8, U9, and U10 (figure

FO-15/4). This divider circuit provides the trigger pulses to the spectrum ana-

lyzer at the rate of one per second. Timing is derived from an available 1.5

kHz signal in the spectrum analyzer which is gated to the divider train (U8, U9,

and U10) by the RS latch, U1 and U3. When an ionogram start signal appears

on U64-3, the output of U1-3 goes high gating the 1.5 kHz signal to U8 where it

is divided by 15 to provide a 1OO-HZ clock to programmable dividers U9 and U 10.

U9 and U10 are programmed to divide the 1OO-HZ signal by 100, providing 1 pulse

per second, stretched by the one-shot U24, to trigger the spectrum analyzer.

The spectrum analyzer returns a sync signal to pins 9 and 10 of U1 (figure FO-

15/4) when it actually starts an analysis scan. Spectrum analyzer scan start

pulses pass through U2-8 to line LC2. This scan start pulse on line LC2 causes

the load buffer gate U1 and U3 (figure FO-15/3) to enable two counter trains (a

divide-by-128 formed by U34, U35, and U36 and a divide-by-100 formed by U46

and U47) and to set line (SLB) enabling memory load buffers in memory load

logic 1A3A2 for inputting new data in the CRT display memory.

4-41. The recirculating CRT display memory is synchronized with the CRT

video. To load data into the display memory, two temporary memory buffers

are provided in the memory load logic 1A3A2. The loading of the temporary

buffers is synchronized with the spectrum analysis scan by a 3.3 kHz clock sig-

nal (SAM) derived from the spectrum analyzer. Clock signal (SAM) (figure FO-

15/3), is divided by 2 in U33 to provide a clock to count the number of bits stored

in temporary buffers. Each display memory is split into an odd and even memo-

ry, and each has a separate memory buffer for data input. U33 pins 9 and 8 al-

ternately enable the output of U33-5 to drive the clocks for the two corresponding

memory buffers (SRE and SRO). Each buffer on 1A3A2 holds 64 bits, making a

total of 128 bits for each CRT display line. The first 100 bits are associated

with the spectrum analyzer data input, while the last 28 bits are associated with

the AGC information provided by the receiver. The counter U34, U35, and U36

divides the spectrum analyzer clock by 128, while the second counter, U46 and

U47, divides the same clock by 100. Both of these counters are held reset at

zero until the synchronizing pulse from the spectrum analyzer (LC2) causes them

to be enabled. At the same instant, the RS latch made up of U62 and U26 enables

digitized data from the spectrum analyzer to pass through U62-3 into the memory

buffers (SSD). When counters U46 and U47 reach the count of 100, the spectrum

data is shut off and the AGC data is allowed to pass through U62-8 into the memo-

ry buffers. When the divide-by-128 counter overflows, the load buffer gate re-

sets, stopping the load buffer action until another pulse appears on LC2.

4-42. The analog spectrum data is converted into digital data by a 1-bit analog-

to-digital converter consisting of U43 and U65 (figure FO-15/3). U43 is a stan-

dard voltage comparator with an adjustable threshold level. All analog data

above the threshold of 3/4 volt causes the output of U43 to be high, while the

data below this level causes a low output. Because of the nature of sample tim-

ing in the two 64-bit memory buffers, a small narrow spike coming out of the

spectrum analyzer could be lost because it would not remain high long enough

to be sampled. Thus, U65 is provided as a pulse stretcher to ensure that all

spectrum threshold-crossing pulses are long enough to remain within 1 clock

4-21