TIMING AND CONTROL ASSEMBLY 1A2A2

TM 11-5820-917-13

the circulating memory in assembly 1A3A1. Logic is provided so that, if the

memory output is high at the point in display where a frequency mark is to appear,

the video output goes off and the frequency mark is displayed as a dark line.

4-37. The CRT memory circuit 1A3A1 (figure 4-7) consists of three sets of dual

18432-bit dynamic memory shift registers which circulate the odd and even bits

of the display. Each dual memory is capable of storing one complete display

picture (sounder data + AGC).

4-38. The CRT assembly 1A7 contains the cathode ray tube and the driver

electronics which are located on a circuit card 1A7A 2 within the module (figure

FO-18). The circuit card is the interface between the video signal and the CRT.

It also provides various CRT controls (e.g., brightness, focus, width) which

can be manually adjusted to counter effects of tube and component aging.

4-39. TIMING AND CONTROL ASSEMBLY 1A2A2 (figures FO-4 and FO-15).

This circuit performs five major functions:

Controls the timing of the CRT memory loading.

Controls the timing of the CRT raster.

c. Provides the interface with the spectrum analyzer (1A1) and the 4028

receiver (2A2) which provide the input for display.

d. Provides a count of the vertical line being displayed to synchronize any

line update.

Generates the numerics for the CRT frequency axis.

All timing is provided by a 12-MHz oscillator (figure FO-15/1). This signal is

divided by 10 at two different points. The divide-by-10 U44 provides a con-

tinuously operating 1.2 MHz master cIock while divider U28 provides a 2-phase

totally during vertical retraces and runs at half speed during the horizontal

retrace to keep the dynamic memory circuits operating and yet conserving unused

memory bits. The dynamic MOS shift register memories require a two phase

clock drive;

the read out clock and

the read in clock. These clocks are

derived from the slave clock divider U28 and gates U8, U39, and U40. The CRT

vertical sync (VS1) available at U40-8 is generated by counting 64,

clocks in

U48 and U51 and setting flip-flop U40-8. This starts the CRT vertical retrace

(Q3-E23) which lasts for 16,

clock periods when U40-8 is reset by U42. When

U 52-U53-U54 have counted 280 vertical scans, flip-flop U55-11 is set, and the

horizontal retrace starts. Because the time for a horizontal retrace is too long

to stop the dynamic memories completely, a half speed (600 kHz) clock is gener-

ated (by U29-U28) to keep the memory alive and yet conserve bit storage. This

enables U49, U52, U50 which counts 512 of the half speed

clocks before clearing

flip-flop U55-11 and ending the horizontal retrace. U60-12 buffers the CRT

horizontal sync pulse (TVS).