RECEIVER TEST CIRCUIT

TM 11-5820-917-13

spectrum analyzer would be a signal moving (sweeping) through the HF band at

the same rate as the receiver. An occasional strong interfering signal resulting in

momentary spectrum analyzer overloads may falsely trigger an auto sync detection.

Therefore, up to three tests are made at each of the 25 (50) steps, to insure posi-

tive chirp signal identification and interference rejection. Once a conclusive

test has been achieved (three consecutive tests with "1" in the same position),

the position of the last "1" recorded in the memory is transferred to an up-down

counter (U50, U57, figure FO-11/3) where it is used to fine slip the receiver by a

proportional amount required to place the detected chirp tone within the normal

500 Hz receiver bandwidth, instead of the auto sync 4000 Hz search bandwidth.

An in-sync (INS) signal is then generated to restore the normal 500 Hz bandwidth

to the receiver and spectrum analyzer. If the tests continue to near the upper

limit of the sweep (i.e., 256 seconds after the start of sweep) without achieving

synchronization, a restoration circuit (U32, figure FO-11/2) resets the slip-

burst cycle to the original start time.

4-21. Each path in the receiver is designed to be individually, automatically

synchronized using the AUTO SYNC switch in conjunction with the SET positions of

the MODE control switch. If the MODE switch is changed from a SET position

while performing an auto sync search, the auto sync function is shut down (U31,

figure FO-11/1). This prevents loss of sync in other paths.

4-22. RECEIVER TEST CIRCUIT . The test circuit performs a rapid check

of receiver sensitivity and power supply parameters. The test circuit is activated

by the front panel TEST switch. When initiated, the test includes a check of

standby battery status, an overall DC power supply check, and an overall receiver

check. The receiver check uses an RF generator to simulate an incoming signal,

then checks to see that the signal appears at the correct frequency and at the

proper amplitude. The DC power supply check is made using two, 8-input NAND

gates (U1 and U2, figure FO-11/4). The voltages checked (+5, -12, +12, and

+29/+35) come from various points in the 6025, and the test is intended only to

indicate whether a malfunction is the result of a wiring or power supply fault.

The power supply test fails when the measured voltages are approximately 50%

in error. The inputs are combined and applied to test gate U8-5. Indication of

battery condition is made by transistors Q3 and Q4 (figure FO-11/4). These

transistors are activated by the TEST switch and are indirectly biased by R 25,

R26, and R27 according to the voltage present. Q3 drives the battery green indi-

cator and is on for all voltages above 18 volts. Q4 drives the battery red indicator

and is on for voltages below 23 volts. Since there is an overlap between the 18

and 23 triggering voltages, this middle condition (indicating satisfactory but

marginal batteries) lights both lamps.

4-23. For receiver sensitivity y test, activation of the TEST switch changes the

4028 receiver input from the antenna to a calibrated, sweeping, RF signal that

results in a fixed, 350 Hz tone at the baseband output of the "receiver. Since

the bandwidth of the spectrum analyzer (which corresponds to the vertical CRT

trace) is 500 Hz, the resulting test output tone (350 Hz) is displayed 7/10ths

up the CRT screen, or .7 x 60 = 42 milliseconds along each sync clock period.

One shots U10 and U3 position a 5 millisecond wide test window, centered 42

milliseconds after the start of the spectrum analyzer scan (or CRT sync clock

period). If the signal is detected in this 5-millisecond wide window, U4-7 goes

4-9