ANALYZER OUTPUT SECTION

TM 11-5820-917-13

the memory tail by the same number of words entered. The six-bit words circulating

in the memory are continuously clocked out at the same 2-MHz into a six-bit, digital-

to-analog converter. This output constitutes a reconstructed analog replica of the

input signal over the last 600 samples received by the memory. The frequency ex-

pansion, or time compression, achieved by the analyzer memory is equal to the ratio

of the rate that data is read out of the memory (two megawords per second) to the

rate that data is written into the memory.

Thus, the frequencies are spread between O and 666 kHz, i.e., the O to 500 Hz is

now translated into 0 to 666 kHz, (0 to 500) x 1333.3 = 0 to 666 kHz.

4-14. ANALYZER OUTPUT SECTION . (figures 4-3 and FO-10). The output

section of the spectrum analyzer processes the analog frequency-expanded signal

and provides a spectrum output of 0 to 5 volts amplitude, 200-line frequency reso-

lution, and 60-millisecond scan time. The 0 to 666 kHz signal from the digital-to-

analog converter is low-pass filtered to remove transition spurs caused by the con-

version process. Following the filter is a heterodyne mixer (U25-U26, figure FO-

10/1). The mixer local oscillator (2.250-2.916 MHz) is derived from a VCO (QI,

figure FO-10/6) driven by a 60-millisecond ramp generator (U 12, figure FO-10/5).

The VCO ramp is essentially equivalent to the CRT display vertical sweep. The

output of the mixer is applied to a fixed bandpass filter with an effective bandwidth

of 3.33 kHz centered at 2.250 MHz. By sweeping the mixer local oscillator between

2.250 and 2.916 MHz, the 0-666 kHz signal is translated to the filter center frequency.

This operation is equivalent to sweeping a 3.33 kHz wide filter over the 0 to 666

kHz range of the frequency expanded input data.

4-15. The mixer output is fed to the 2.25 MHz IF processor (figure FO-10/2) and

is mixed with 2 MHz. The resulting 250 kHz difference is fed to the gain weighter

circuit. The gain weighter (Q7, figure FO-10/3) reduces spurious sidebands on the

analyzed signal caused by the data discontinuity at the memory tail (the point where

the oldest and newest samples in the memory meet). The sampling filter is a high

Q active bandpass filter (C60, L3, Q1O, figure FO-10/3) centered about 250 kHz

and having an effective bandwidth of 3.33 kHz. This circuit linearly integrates

energy at 250 kHz within its bandwidth over the 300 microsecond memory recircula-

tion time. At the end of the 300 microsecond memory recirculation, a small sample

is taken at the positive peak of the 250 kHz waveform. It is the voltage amplitude

of this sample, which represents the energy in the filter over the last 300 micro-

seconds, that is used to measure spectral amplitude. At the end of the 300 micro-

second period the resonant circuit is quenched (Q11) and the process is repeated.

4-16. The output sample and hold circuit works in conjunction with the sampling

filter and supplies the peak voltage data. The output of the sampler (Q16, figure

FO-10/3), consisting of stepped samples of the signal waveform, is fed to a low pass

spectrum filter for final smoothing before being sent to the CRT display logic circuits.

4-17. RECEIVER CONTROL SECTION

4-18. AUTO SYNC 1A5 (figure FO-11). The auto sync circuit performs the logic

functions for automatic time synchronization of the receiver system. Also, a part

of the assembly contains the logic circuits to perform the receiver test which is

described in paragraph 4-22. The function of the auto sync is to relieve the

operator of the task of critical initial synchronization between the receiver and

TSC-4B transmitter. In practice, the operator is required only to time the units

to within

- second of each other after which the auto sync circuit searches for,

and locks onto the chirp signal. Then, it fine adjusts the timing to synchronize

the chirp signal within the receiver analysis window.

4-6