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TM-11-5820-695-35
and has no effect on U4.  When an out-of-range
zero when the CVDOW signal and the 32 kHz clock are
condition is detected, the +12 Vdc signal from U7A-12
the phase; it is applied to oscillator U1 through R37 at
turns on Q1. With Q1 on, a low impedance bypass path
pin 6. This control voltage causes the frequency of U1
through Q1 shorts the feedback network (R11, C11,
to track with CVDOW timing. If the ERR pulse is wider
C12) of U4. This sets U4 to mid-range and the phase
than the FEF pulse, the net charge in C8 and the
detector starts hunting again for sync between CVDOW
voltage at U4-4 increases.
The output at U4-10
and the 32 kHz clock. As the varying output of U4 is
increases.  The output at L4-10 then decreases and
processed by U7A and U7B, the input level at U7A must
causes the oscillator frequency to increase.
The
fall within +1 Vdc ((5) above) before the output atU7A-
opposite reactions occur when the ERR pulse width
12 returns to the normal -12 Vdc. When this occurs, Q1
decreases. U4 also acts as a low pass filter to smooth
turns off and normal phase detector loop operation
out changes in the oscillator control signal. The signal
resumes.
at U4-10 normally varies between 7 Vdc.
(4) The output signal from U10-4 is also
(6) The retimed CVDOW signal from U5B-9
applied to the inverting input of voltage comparator U7B
((2) above) is applied to status monitor U8 and to U11A.
which is used as an analog inverter.  U7B and U7A
U8 is in the set state as long as the CVDOW signal is
together act as an out-of-limits detector.  When the
active. Logic 0 from U8-12 at UlIA-2 has no effect and
phase difference between CVDOW and the 32 kHz
U11A passes the CVDOW signal. In digital orderwire
clock is within limits, the output at U4-10 is within the
mode, OW SEL switch lA12Sl (P-10) applies logic O at
range +7 Vdc. When this voltage is in the minus range,
U1IB, so logic 1 from U8-5 holds the output of U11B at
it is passed by diode CR5. When it is in the positive
Logic 0.  Signal CVDOW RPLL FAIL is then logic 0
range, it is inverted by U7B and passed by diode CR4.
(normal) and status indicator CR10 is off.  If the
In either case, normally, a negative voltage of 7 volts or
CVDOW signals fails, U8 times out and resets, so logic
less is applied through R18 to U7A-1.  The normal
1 from U8-12 clamps UllA-1 at logic O. U8-5 applies
output voltage at U7A-12 is -12 Vdc. This voltage and a
logic 0 at U11B, which has logic 0 input also from Pl-10.
supply of -12 Vdc at R30 combine through the resistor
The U11B output and signal CVDOW RPLL FAIL are
network R28 through R33 and CR6 to produce a signal
then logic 1 (fault), and indicator CR10 turns on. If an
between 0 and -7 Vdc at U7A-2. As long as the control
out-of-range condition is detected ((5) above), U8 is
voltage from U4-10 is within the +7 Vdc limits, the signal
reset and the same fault indications occur as those
at U7A-12 is -12 Vdc.  If this voltage exceeds these
described for failure of the CVDOW signal. In analog
limits, the output at U7A-12 switches to +12 Vdc. The
orderwire mode, the signal at U18B from Pl-10 is logic
voltage at U7A-2 then switches to -1 Vdc. The signal at
1. The output of U11B is then clamped in the logic 0
U7A-12 is connected through R32 and inverter U9A to
state (normal) and status indicator CR10 is off.
the clear input (pin 11) of status monitor U8 ((7) below).
e. Digital Orderwire Demultiplexer lA1247 (fig. 5-
(5) The output at U7A-12 is applied through
8.3 and 5 .9). Digital orderwire demultiplexer 1A127
R13 to transistor Q1, the out-of-range reset control.
receives the retimed CVDOW signal and its 32 kHz
Normally the signal applied to Q1l is -12 Vdc; Q1 is off
clock signal from module A6. In module
Change 6 2-24.8


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