Digital Orderwire Demultiplexer lA1247-continued

TM-11-5820-695-35

CVDOW signal are DVOW bits. The CVDOW signal is

A7, the CVDOW signal is demultiplexed to obtain its two

applied to a demultiplexing flip-flop. It is clocked

components, 16 Kb/s CVOW and 2 Kb/s DOW. The

through the flip-flop by a 16 kHz signal derived from the

DVOW and DOW signals are routed to the OCU. These

32 kHz CVDOW clock. Since the clocking rate (16

output signals are monitored to generate status signal

kb/s), is one-half the CVDOW bit rate (32 kb/s), one or

OWDMX FAIL WHICH is routed to module A2. Module

the other of the two alternate sequences of bits in

A7 is used only in digital orderwire mode. A control

CVDOW is passed through the demultiplexing flip-flop.

signal from OW SEL switch lA12Sl inhibits the status

If the 16 kHz clock is phased to the wrong sequence of

signal and prevents an alarm status indication in analog

bits in CVDOW (DOW instead of DVOW), a simple 180

orderwire mode when there is no CVDOW signal.

degree phase inversion of the 16 kHz clock will phase it

(1) In the 32 kb/s CVDOW signal, alternate

to the correct bit sequence.

bits are DVOW and DOW signal bits. The sequence of

alternate bits comprising the DVOW signal is random

(e) The DOW demultiplexing process is

and unpredictable, but the sequence of alternate bits

more complex. The CVDOW signal is clocked through

comprising the DOW signal has known characteristics.

the DOW demultiplexing flip-flop by a 2 kHz clock

These characteristics of the DOW signal provide the

derived from the 32 kHz CVDOW clock. Since the

work ing basis for the demultiplexing process.

clocking rate (2 kHz) is one-sixteenth the CVDOW bit

rate (32 kb/s), only every 16th bit in CVDOW is passed

(a) The DVOW bit rate is 16 kb/s so

by the DOW demultiplexing flip-flop. To assure the

alternate bits in the 32 kb/s CVDOW signal are DVOW

correct DOW signal, the 2 kHz clock must be synced to

bits.

DOW signal transitions ((b) and (c) above). Then, for

(b) The DOW signal bit rate is 2 kb/s

DOW logic 0, Fe demultiplexing flip-flop will pass a logic

but one DOW bit is redundantly represented by eight

0 (the first bit in the redundant DOW logic 0 sequence).

consecutive alternate bits in the 32 kb/s CVDOW signal.

For logic 1, it passed a logic 1 (first bit in the redundant

DOW logic 1 sequence).

logic 0 is 01010101, and for logic 1, the pattern is

(f) Both demultiplexing processes (s

10101010.

Thus the DOW bits in CVDOW are

and (e) above depend on first establishing e correct

alternating l's and O's, except at DOW signal transitions.

phase for the 16 kHz.

At transitions from logic 0 to logic 1, there are two

(2) The CVDOW signal (P1-B, from module

consecutive l's (the last bit of the DOW logic 0 and the

A6) is inverted in U4 and applied to 5-stage shift register

first bit of the logic 1). At transitions from logic 1 to logic

U2/U1. The 32 kHz signal (P1-H, from A6) is inverted in

0, there are two consecutive O's in the DOW signal

U4 and applied to the shift register, to a divide-by-2 flip-

(remember they are alternate bits in CVDOW) mark

flop at U1-9, and to CLK input (pin 14) of up/down

DOW signal transitions because that is the only time this

counter U3. The output at U5-1 (16 kHz) is applied to

condition can occur.

pin 1 of Exclusive-OR gate U5. The signal at U5-5 is

(d) The DVOW demultiplexing process

normally logic 1. If the signal at U5-4 (and U1-3 and

is basically simple because alternate bits in the 32 kb/s

Change 6 2-24.9