Digital Orderwire Retimer

TM 11-5820-695-35

to USA and U2A. The CVDOW signal is retimed in U5A

for sync between data and clock signals. After 150

and 8 Clock C1. The output at U5B-9 is connected to

msec, U20B resets, U1 turns off and operation of U4

UllA-3. The signal at UllA-2 is normally logic 1 ((7)

returns to normal.

below) and the RETIMED CVDOW signal at UllA-1 is

(11) The retimed data signal from U12B-8 is

routed through Pl-12 to module A7.

applied to activity detector U20A. As long as the data

signal is active, U20(A is set and logic 1 from U20A-13,

(2) IC's U2 and U3 comprise the transitional

inverted in U1OE, makes the DRPLL FAIL signal logic 0

phase detector. The input signals at U2A are the

(normal). Logic 0 from U20A-4, inverted to logic 1 in

CVDOW signal and the same signal inverted (U2A-2)

U16B, holds indicator CR12 off (normal). If the data

from U5B-6. The signal at U5A-6 is clocked through

signal fails, U20A times out and resets. If an out-of-

USA by clock C1. If clock C1 is exactly in phase with

range condition is detected by U20B ((10) above), a

transitions of the CVDOW signal, the signals at U2A-1

logic 0 at U20A-2 resets U20A. In either case, the logic

and -2 will always be opposites (logic 1 and logic 0) and

signals reverse: DRPLL FAIL is logic 1 (fault) and

U2A-3 will be logic 1. If there is a phase difference

indicator CR12 turns on.

between clock C1 and CVDOW transitions, the signals

at U2A-1 and -2 will sometimes be the same. U2A-3 will

d. Digital Orderwire Retimer (1A12A6 (fig. 5-8.3

be logic 0 at those times. This is the phase detector

and 5-38.8). The principal function o-f digital orderwire

error signal and its duration is proportional to the phase

retimer lAl2A8 is to retime the CDVOW signal. To

difference between CVDOW and clock C1. The retimed

accomplish this, a CVDOW clock signal is generated in

CVDOW signals from USA-5 and U5B-9 are applied to

a phase lock loop by extracting timing from the CVDOW

U2B and the output is ANDed with clock C2 in U3B.

signal ((2), (3), and (4) below). The RETIMED CVDOW

This is the REF signal with constant width equal to one

and CLOCK SIGNALS are routed to module A7. The

cycle at 32 kHz. When the ERR signal (U3A-12) goes

retimed.CVDOW signal and the phase lock loop are

positive, it charges capacitor C8 through CR1, and when

monitored to generate a status signal. The status signal

the REF signal (U3B-6) goes negative it discharges C8

is routed to module A2. These activities occur only in

through CR2. The net charge in C8 at any time is

digital orderwire mode.

proportional to the difference in width between the ERR

(1) The timing is extracted from the CVDOW

and REF pulses. This difference is proportional to the

signal and used in a phase lock loop to synchronize the

phase difference between clock C1 and the timing of the

frequency of oscillator U1. Oscillator U1 generates a 64

CVDOW signal.

kHz signal at Ul-13. This signal is inverted to U3C and

(3) A reference voltage (2.5 Vdc) is applied to

divided by 2 in U6A to provide the 32 kHz clock C1.

pin 5 of voltage comparator U4. The voltage is

The 64 kHz signal is applied through buffer U2D to U6B.

developed from +5 vdc through R7, R8 and R9 and is

U2D provides a time delay equal to that of U3C, so

filtered by C9. Variable resistor R9 is adjusted to set the

inputs to U6A and 8 are exactly 180 degrees out-of-

level. The voltage across C8 is applied to inverting

phase. The signal at U6B-9 is 32 kHz clock C2; it lags

input V4-4 through isolating resistor R1O. The output

90 degrees behind clock C1. The SLICED CVDOW

voltage at U4-10 is approximately Change 6

signal (from module A8) is inverted in L2C and applied

Change 6 2-24.7