The balanced SLICED DATA signal

TM 11-5820-695-35

occurring at clock rate. This is the REF signal. When

through to U14-8; and the signal from U15-6 at U14-5 is

the ERR signal goes positive, it charges C35 through

connected through to U14-6. For rate 18.72, the clock

CR10 and when the REF signal goes negative it

signal is taken directly from U19 (it is not divided) and

discharges C35 through CR11. The net charge in C35

applied at U14-1 and -2. For all rates, the outputs at

at any time is proportional to the phase difference

U14-8 and -6 are complementary clock signals at the

between the ERR and REF signal pulse widths. This

selected rate. Switching operation of U14 is controlled

difference is proportional to the phase difference

by the signals at pins 3, 4, 9, and 13. For all rates

between the data and clock signals.

except 18.72, the signals at U14-4 and -9 are logic 1;

they switch to logic 0 for rate 18.72. For all rates except

(9) A reference voltage (+2 Vdc) is applied to

18.72 the signals at U14-3 and -13 are logic 0; they

pin 5 of voltage comparator U4. The voltage is

switch to logic 1 for rate 18.72.

developed from +5 Vdc through R37, R38 and R39 and

(7) The balanced SLICED DATA signal from

is filtered by C36. Variable resistor R39 is adjusted to

module A8 at P1-2 and -3 is converted to TTL level in

set the level. The voltage across C35 is applied to

line receiver U3. Resistors R18 and R19 are line

inverting input U4-4 through isolating resistor R34. The

terminations. The data signal from U3-13 is retimed in

output voltage at U4-10 varies in the range +4 Vdc for

U12A by the clock signal from U14-6. The retimed data

the normal range of phase difference in the data and

signal at U12A-6 is routed through buffers U17A and

clock signals. This signal is applied to varactor diode

U13D to module A4 (REGEN DATA, Pl-M) and to

CR5 through a low pass filter as described in (2) above.

module A8 (REG DATA, Pl-10). The clock signal from

(10) The output at U4-10 is also applied to

U14-8 is routed through buffer U17B to module A4

voltage comparators U9A and B which are used as an

(RCOVD TMG, P1-12).

out-of-range detector. Resistor network R41, R44 and

(8) U12A and B, U13A, B, and C and U16A

R45 applies reference voltages of +8 Vdc at U9A-4 and

comprise a phase detector. The input signals at U13B

-8 vdc at U9B-ll. For the normal range of phase

are the data signal from U3-13 and the retimed data

difference, the outputs at U9A-15 and U9B-8 are high.

signal (inverted) from U12A-6. Buffer U13A provides a

This signal is applied to monostable U20B which is

slight delay for the signal at U13B-4 to compensate for

normally reset with logic 0 at U20B-12. If the phase

the delay incurred by the signal at U13B-5 in passing

difference exceeds the normal limits, the outputs at U9A

through U12A. If the clock signal from U14-6 is exactly

and 8 switch to low. This transition sets U208B and

in phase with transitions of the data signal from U3-13,

U20B-12 changes to logic 0. The signal from U20B-12

the signals at U13B-4 and -5 will always be opposites

is applied to electronic switch U1. When the signal at

(logic 0 and logic 1) and U13B-6 will be logic 1. If there

U1-5 and -10 is logic 1, U1 is off and has no effect on

is a phase difference, the signals at U13B-4 and -5 will

U4. When 'J1-5 and -10 switch to logic 0, U1-13 and -

sometimes be the same. U13B-6 will be logic 0 at those

14 are connected together and also Ul-l and -2. The

times. This is the phase detector error signal and its

short at U1-1 and -2 discharges the feedback network of

duration is proportional to the phase difference between

U4; the short at Ul-13 and -14 applies +5 vdc through

data and clock signals. The retimed data signals from

R31 and R34 to U4-4. The output voltage at U4-10 is

U12A-5 and U12B-9 are applied to U13C and the output

then approximately 0 Vdc and oscillator U18 is driven to

signal at U13C-8 is ended with the clock signal in U16A.

center frequency. The phase detector starts searching

The output at U16A-6 is a constant width negative pulse

again

Change 6 2-24.6