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TM 11-5820-695-35
logical complement of the signal at pin 9. The signal
clock signal (OR4915). The output of the function logic
status of pins 8 and 9 remains fixed until the next trigger
switch at NAND gate A5A is the 1RPCM signal.
pulse. The logic 0 output (pin 8) is connected to the D
(b) When signal OTEST is logic 0 and
input (pin 12) of A3B and to pin 13 of NAND gate A2D
signals TC1 and TC2 are logic 1, the output of NAND
(waveform E, fig. 5-38.1).  The logic 1 output is
gate A5B provides a logic 1 at pin 3 of NAND gate A5A.
connected to pin 9 of NAND gate A2C. When either
Signal TC2 provides a logic 1 input to inverter A6C
A2C or'A2D has logic 1 at both inputs, its output goes to
which then provides a logic 0 input to inverter A5C.
logic 0 (ov). This condition can never occur for both
Inverter A5C then provides the second fixed logic 1 at
NAND gates at the same time since they receive
the input of A5A (pin 2). NAND gate A4B has a logic 1
complementary inputs from A3B. When A2C has logic
at pin 6 from A6D and at pins 7 and 9 from TC1 and
1 at both inputs, A2D has a logic 0 at pin 13, so the
TC2. So signal OCLPCM passes through inverter A6B,
output of A2C is Ov (waveform F, fig. 5-38.1) and the
and NAND gates A4B and A5A.  The output of the
output of A2D is +5v (waveform G, fig. 538.1). The
function logic switch is the OCLPCM signal.
+5v output of A2D matches the +5v at the center tap of
(c) When signals OTEST and TC1 are
the primary of transformer T1, so no current flows
logic 0 and TC1 is logic 1, the outputs of NAND gates
between terminals 3 and 4. The ground at the output of
A5B and A4B are logic 1 because of the OTEST and
A2C causes current to flow between terminals 1 and 2
TC1 signals, respectively.  The output of NAND gate
from the +5v at the center tap. This induces a positive
A5C is logic 1 because of signal OTEST, inverted in
pulse in the secondary of T1 (waveform H, fig. 5-38.1).
A6D. Thus NAND gate A5A has three logic 1 inputs and
When conditions are reversed and A2C has a +5v
the output of the function logic switch is a fixed logic 0
output and A2D has ground output, a pulse of the
(no signal).
opposite polarity is induced in the secondary of T1.
(d) When the OTEST, TC1 and TC2
Thus the standard logic pcm signal is converted into
signals are all logic 0, NAND gate A5B provides a logic
bipolar form.  In figure 5-38.1 the logic 1 pulses of
1 input to NAND gate A5A at pin 3, and NAND gate A4B
waveform A are labeled A through E and the
provides a logic 1 at pin 1. NAND gate A6A has a logic
corresponding bipolar pulses are identified by the same
1 at pin 1 so it gates the clock signal (OR49152) to the
letter in waveform H.
trigger input of flip-flop A3A. Flip-flop A3A divides the
(3) The bipolar pcm signal at the secondary
clock signal by two and sends a 2457.6 kHz signal to pin
of T1 is fed through the equalizer (cable simulation
11 of NAND gate A5C. This gate has logic 1 on pins 12
network). The overvoltage shunt circuit protects circuits
and 13 from signal TC2 inverted in A6C and signal
of radio digital processor AA16 against input voltage
OTEST inverted in A6D.  So the 2457.6 kHz clock
surges from the cable. The pulse shaper circuit (L2-
signal is the output of the function logic switch at NAND
R14) improves the waveshape of the output signal. The
gate A5A.
orderwire and cable direct current signal (OW1, pin A) is
(2) The output signal of the function logic
connected through the pulse shaper and overvoltage
switch is applied to the trigger input of monostable
circuits and combined with the pcm signal. The output
multivibrator Al.  Monostable multivibrator Al is the
signal, designated TOCX is routed to the TO CABLE
pulse width gate; it accurately sets the pcm signal pulse
jack, J5.
width at 407 nanosec (48-channel) or 203 nanosec (96-
(4) The bipolar pcm signal is connected to the
channel). It triggers on the positive-going edge of the
cable traffic circuit by means of an auxiliary secondary
trigger signal and the timing is determined by resistor R3
winding (pins 5 and 6) on transformer T1. The signal is
and capacitor C1. The output signal of Al (waveform A,
then rectified and filtered in a voltage doubler rectifier
fig. 5-38.1) is applied through inverter A2B waveform B,
filter circuit (C11, C12, CR7, CR8, R15 and R16).
fig. 5-38.1 to one input of NAND gates A2C (pin 10) and
When traffic is active, the positive voltage output of the
A2D (pin 12) in the bipolar cable driver. From A2B, the
rectifier circuit forward biases transistor Q1.  Current
signal is also applied to the trigger input of flipflop A3B
flow in the collector load resistor of Q1 (R17) then
via NAND gate A2A (waveform C, fig. 5-38.1). Flip-flop
forward biases transistor Q2.  Resistor R19 is the
A3B triggers on the positive going edge of the trigger
collector load resistor for Q2.  The positive voltage
signal and transfers the logic signal then present at input
developed across
D to the TM 11-582069535 logic 1 output (pin 9)
(waveform D, fig. 5-38.1).  The, signal at the logic 0
output (pin 8) (waveform E, fig. 5-38.1) is always the
Change 2
2-20.1


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