Radio Control-Comparator 1A12A9 Asynchronous Mode

TM 11-5820-695-35

kHz signal. A logic 1 signal is present at pin 8 of A5C

A10 is inverted twice by the lamp driver (inverter A2A

and the 4915.2 kHz signal can pass. Thus the selected

and Q4), so signal 1RCFAIL is low (logic zero) and lamp

clock signal is routed through A4C and A4B to the

DS1 is lighted. However, when correction is required,

trigger input of pcm retiming flip-flop A8 and to the clock

the output of Al can vary from +3 volts to -3 volts.

pulse generator (waveform C, fig. 5-37.1). For the

Positive/negative clamp detector A10 detects output

remainder of the discussion of 'synchronizing, see b(l)(b)

signals of Al that exceed the indicated limits. When

through b(l)(f) above, which apply also to operation in

either limit is exceeded the output of A10 goes high.

the asynchronous mode.

This signal, inverted twice by the lamp driver, is sent to

alarm monitor 1A12A5 and also turns off lamp DS1.

(2) Retiming. The 2457.6 kHz clock (48

(2) Retiming. The 2304 kHz radio-to-cable

CHAN) or the 4915.2 kHz clock (96 CHAN) whichever is

clock signal (waveform C, fig. 5-37) is applied to the

selected by the ADDM TRAFFIC SELECT switch is

trigger input of pcm retiming flip-flop A8 and the

applied to the trigger input of pcm retiming flip-flop A8

1RSPCM-2 signal (waveform D, fig.

(waveform C, fig. 5-37.1).

The IRSPCM-2 signal

(waveform D, fig. 5-37.1) is applied to the D input.

5-37) is applied to the D input. Operation of flipflop A8

Operation of flip-flop A8 is similar to operation of A9 ((1)

is similar to operation of A9 ((1) (a) above). Signal

above). Signal 1RSPCM-2 is retimed by the 2457.6 kHz

1RSPCM-2 is retimed by the 2304 kHz radio-to-cable

or 4915.2 kHz clock. The output signal (waveform E,

clock. The output signal (waveform E, fig. 5-37) is sent

fig. 5-37.1) is sent to radio digital processor 1'19,A16.

to radio digital processor 1A12A10.

(3) Baud Generators. The duration of the

b. Radio

Control-Comparator

1A12A9,

baud pulse generated by 48-channel ddm baud

Asynchronous Mode (fig. 5-8.1 and 5-37.1). Radio

generator A6 is determined by the current drive supplied

control-comparator 1A12A9, synchronizes the frequency

by the +5vdc supply and time constant components

of the 9830.4 kHz radio-to-cable clock signal with the

C13, R32 and R33. For asynchronous operation, the

frequency of the pcm signal and it retimes the pcm

baud pulse duration is changed to 407 nanoseconds (48

signal.

CHAN) or 203 nanoseconds (96 CHAN).

This is

(1) Synchronizing. Radio control comparator

accomplished by enabling the 48-channel addm baud

1A12A9 receives the 9830.4 kHz radio-to-cable clock

generator Q5 or the 96-channel baud generator Q6.

signal from 9830.4 kHz vco lA12All and the reshaped

These addm baud generators supply additional drive

pcm signal from radio digital regenerator 1A12A8. The

current to the 48-channel ddm baud generator and thus

9830.4 kHz radio-to-cable clock signal (0R98304) is

change the duration of the baud pulse output of A6 as

applied to the trigger input of clock counter flipflop A9A

required. When the ADDM TRAFFIC SE.LECT switch

which triggers on the positive-going transition of clock

is in the 48 CHAN position, the input at pin 4 is +5v,

pulses (waveform A, fig. 5-37.1). Each time A9A is

diodes CR15 and CR16 are reverse biased and there is

triggered, the logic one output (pin 5) takes on the logic

no current flow in resistor R28. Transistor Q6 has +5vdc

state of the signal present at input D (pin 2) at that time.

at base and emitter and is at cutoff. The input at pin 5 is

The output at pin 6 is always the complement (logical

Ov (ground) and current flow through diodes CR13,

opposite) the output at pin 5. The output state of A9A is

CR14, R25, and R26 forward biases transistor Q5.

then maintained until the next trigger pulse. As a result,

Transistor Q5 delivers current through resistors R30 and

A9A divides the input signal by two and provides output

R31 to A6 to change the baud pulse duration. When the

signal 4915.2 kHz cable-to-radio clock (waveform B, fig.

ADDM TRAFFIC SELECT switch is in the 96 CHAN

5-37.1) which is sent to radio digital processor I 1A2A16

position the input at pin 4 is Ovdc and the input at pin 5

and to NAND gate A5C. When the ADDM TRAFFIC

is +5vdc. Transistor Q5 is then turned off and Q6 is

SELECT switch is in the 48 CHAN position, the input

turned on and the 96-channel baud pulse is generated.

signal at pin 9 is logic 1 (+5v) and the signal at pin 10 is

c. Radio Digital Processor 1A12A10, Synchronous

logic 0 (grd). The clock signal is divided by two again in

Mode (fig. 5-8 and 5-38). Radio digital processor

A9B and this 2457.6 kHz signal can now pass through

1A12A10 receiver the full baud, retimed pcm signal

NAND gate A5D, which is enabled by the logic 1 at pin

(1RPCM) from 1A12A9 and

13. The 4915.2 kHz signal from A9A is blocked at A5C

which has logic 0 at pin 8. When the ADDM TRAFFIC

SELECT switch is in the TM 11-5820-695.-35 96 CHAN

position, A5D has logic 0 at pin 13, blocking the 2457.6

Change 2

2-19