The output (E7) of the delay circuit

TM 11-5820-695-35

Thus, 1PP remains low and positive pulses to the

phase comparator A2B, A2C (waveform OFP, fig. 5-

integrator are not generated. Also, 1BP remains low, so

37). The 2304 kHz radio-to-cable clock signal is applied

ONP is high and negative pulses to the integrator are

directly to one input (pin 1) of NAND gate A3A in the

not generated.

clock pulse generator and to the other input (pin 2)

through inverters A3C, A3D and A3B. Because of the

(e) The output signal of differential

propagation delay through the three inverters, the input

integrator Al is connected to the frequency control input

signals to A3A are simultaneously logic one only for a

of 4608 kHz vco 1A12A11. When the input to A1 is a

short time immediately following a positive-going

positive pulse, the output is a negative-going change in

transition at the output of A4B. The resulting logic zero

voltage. When the input is a negative pulse, the output

output of A3A resets phase comparator A2B, A2C

is a positive going change in voltage. This means that

(waveform OFP, fig. 5-37). Thus, phase comparator

the output voltage starts to rise (or fall) at a fixed rate of

A2B, A2C is set by the leading edge (positive-going

change (slope).

When clock and data are in

transition) of data pulses and reset by the leading edge

synchronism, positive and negative pulse inputs to A1

of clock pulses. The difference in time between set

are approximately equal, and the positive and negative-

(ODP) and reset (OCP) pulses to the phase comparator

going changes in output voltage cancel since the slopes

is a measure of the phase difference between data input

are equal. These low amplitude excursions of the

1RSPCM-2 and clock input OR4608.

output signal are filtered at the input of 1A12A11 and

the output frequency remains constant. When the

positive pulse inputs to A11 are longer than the negative

circuit in the data pulse generator (6(b) above) is also

pulses, the negative-going output caused by the positive

connected to baud generator A6 which is a nonstable

pulse is not entirely canceled by the return in the zero

multivibrator. It generates a positive output pulse each

direction caused by the following negative pulse. The

time the input signal goes to logic zero. The duration of

net result is that the signal remains negative and will go

the positive pulse is adjusted so that the total time from

more negative as long as this condition (longer positive

the start of ODP to the end of the baud pulse is 4d4

pulses) holds. However, the negative output signal

nanoseconds. This signal is applied as one input (1BP

causes the frequency of 1A12A1 to increase, clock

to AND gate A7B (waveform, 1B-P fig. 5-87).

pulse OCP then occurs sooner and positive pulses are

shortened and the length of negative pulses is

(d) The output signal of the phase

increased. This action and reaction occurs until positive

comparator (OFP) (waveform, OFP fig. 5-37), which

and negative pulses are equal. When the negative

represents the phase difference between data and clock

pulses are longer than positive pulses, the same kind of

signals, is inverted by inverter A7A. The output signal

action in the opposite direction takes place. The output

of inverter A7A (waveform, 1PP fig. 5-37) causes the

of A1 goes positive, clock frequency is decreased and

positive pulse generator to generate the positive pulse

clock pulse OCP is delayed. This shortens the negative

input to differential integrator A1. The output of the

pulses. The result is that the output of A1 always

baud generator (1BP) and the output of the phase

produces a frequency change at 1A12A11 that tends to

comparator (OFP) are applied to AND gate A7B. The

equalize positive and negative pulses and when equality

output of AND gate A7B (waveform, ONP fig. 5-37)

is established to maintain it. When the data signal has

causes the negative pulse generator to generate the

logic zero bits, neither positive nor negative pulses are

negative pulse input to differential integrator A1. Thus,

sent to integrator A1, however, it has a long time

at the start of each data pulse (corresponding to a logic

constant which holds its output to bridge over these

one bit in the data signal) ODP goes negative, OFP

short intervals.

goes negative and 1PP. This condition holds and is a

positive pulse goes positive. Input to the integrator is

(f)

The output of differential

generated until OCP goes negative. When OOP goes

integrator A1 is also connected to positive/negative

negative, OFP goes positive and since 1BP is positive,

clamp detector A10. Normally, the output of differential

ONP goes negative.

This condition holds and a

integrator Al is close to zero volts as it holds the clock

negative pulse input to the integrator is generated until

signal in synchronism with data. The output of A10 is

1BP goes negative. When zero bits occur in the input

then low. The low output from

signal (1RSPCM), ODP remains high and the phase

comparator flip-flop is not set, so OFP remains high.

2-18