Traffic alarm circuits.

TM 11-5820-695-35

of 420 nanoseconds and is otherwise similar to transition

pulse before it times out (350 microseconds), the timing

detector 1 (A9). A10 provides a low (logic zero) output

cycle starts over again. Thus, as long as pcm trigger

at pin 6, as long as it receives input signals from A6.

pulses occur at ]east once every 960 microseconds, the

Voltage comparator A8 then provides a logic one output

output of A6 is held at logic one (pin 8). The logic one

and this is inverted to logic zero by A3E. When the pcm

output at pin 8 is inverted by lamp driver Al and

signal fails, the tuned circuit no longer receives inputs

provides a logic zero (low) at lamp DS1. Lamp DS1 is

with the timing required to sustain oscillation, A10 times

then lighted. Pin 6 of A9 of this time has logic zero

out and the output at pin 6 goes to logic one. Output

output. This signal (1RRFAIL) is sent to alarm-monitor

signal 1FRFAIL then becomes logic one to indicate

1A12A5. If A9 times out, the outputs become logic zero

failure of the FRPCM signal.

(pin 8) and logic one (pin 6). Lamp DS1 goes out and

1RRFAIL indicates failure (logic one).

Radio

Control-Comparator

1A12A9,

(2)

Traffic alarm circuits.

Synchronous Mode (fig. 5-9 and 5-37). Radio control-

comparator 1A12A9 synchronizes the frequency of the

(a) The FRPCM signal is applied to

4608 kHz radio-to-cable clock signal with the frequency

slicer 1 (A7) which has a fixed reference voltage at the

of the pcm signal and it retires the pcm signal.

other input. A7 is a high speed differential comparator

and it compares the signal (FRPCM) with the reference

(1) Synchronizing.

Radio

control-

voltage. It produces a pulse output with a steep vertical

comparator 1A12A9 receives the 4608 kHz radio-to-

rise for negative going voltage transitions at the input

cable clock signal from 4608 kHz vco 1A12A11 and the

and a sharp vertical drop for positive-going transitions.

reshaped pcm signal from radio digital regenerator

Thus, the input signal is sliced into separate voltage

1A12A8.

pulses corresponding to the logic ones in the FRPCM

signal.

(a) The 4608 kHz radio-to-cable

clock signal (OR4608) is applied to the trigger input of

(b) The square wave output of A7

clock counter flip-flop A9 which triggers on the positive-

is applied to both inputs of nand gate A4C in the leading

going transition of clock pulses (waveform A, fig. ,37).

edge pulse generator; directly to pin 9 and through delay

Each time A9 is triggered, the logic one output (pin 5)

inverters A5A, A5B and A5C so pin 8. Because of the

takes on the logic state of the signal present at input D

propagation delay through the three inverters, the input

(pin 2) at that time. The output at pin 6 is always the

signals to A4C are logic one simultaneously only for a

complement (logical opposite) the output at pin 5. The

short time immediately following a positive going

output state of A9 is then maintained until the next

transition at the output of A7. The output signal of A4C

trigger pulse. As a result, A9 divides the input signal by

is a series of short duration pulses (logic one) that

two and provides output signal 2304 kHz cable-to-radio

correspond in frequency with transitions of the input

clock (waveform B, fig. 6-37) which is sent to radio

signal (FRPCM).

digital processor 1A12A10 and to NAND gate A5C.

Gates A5C, A5D and A4C and flip-flop A9B are included

for use in a future application. A9B and A5D are not

applied, through inverters A4D and A1, to a tuned circuit

used and A5C and A4C act as inverters. The 2304 kHz

with a crystal filter. The resonant frequency of the tuned

radio-to-cable clock signal from pin 6 of A9 is inverted

circuit and crystal is the pcm signal frequency, 2304

by A6C, A4C and A4B and applied to the trigger input of

kHz. The applied pulses cause the tuned circuit to ring

pcm retiming flip-flop A8 and to the clock pulse

or oscillate, but only at its own frequency, and if the

generator (waveform C, fig. 5-7).

frequency of the pulses differs too much from the tuned

circuit frequency, oscillation is not sustained. Thus, the

(b) Signal 1RSPCM-2 is applied

tuned circuit rejects small timing errors caused by noise

directly to one input (pin 5) of NAND gate A5B in the

pulses and distinguishes between the normal pcm signal

data pulse generator and to the other input (pin 6)

and a random noise-pulse-only condition that exists

through delay inverters A5A, A4D and A4A. Because of

when the pcm signal is lost.

the propagation delay through the three inverters, the

input signals to A5B are simultaneously logic one only

(d) The output signal from the

for a short time immediately following a positive-going

tuned circuit is applied to slicer 2 (A6) which is similar to

transition of the pcm signal (ODP waveform, fig. 5-7).

slicer 1 (A7). The square wave output of A6 is applied

The resulting logic zero output of A5B sets

to transition detector 2 (A10) which has a time constant

Change 1 2-17