The descrambler circuit

TM 11-5820-695-35

causing the RCOVD DATA to remain unchanged when

B7 and B15. If 87 and B15 are logical opposites (0, 1 or

clocked into U6A-2.

1,0), the data bit at U11A-2 appears at U11A-3

unchanged and is clocked into U8A-2. If B7 and B15

(3) An individual flip-flop may be set or

are logical equals (0,0 or 1,1, the data bit U11A-2 is

reset when power is first turned on; the initial state is

inverted and then clocked into U8A-2. The logic action

random unless means are provided to predetermine it.

is explained in the truth tables above for exclusive OR

Thus for the flip-flop of the 15-stage shift register, any

gates U11D and U11A. Columns 1 and 2 show the

distribution of 1's or 0's could result at power turn-on,

possible logic states for B7 and 815. Columns 2 and 3

including a state of all 1's or all 0's. A state of all 1's or

show the inputs to U11D and column 4 shows the

all 0's is called a lockup state because if it occurred, and

corresponding output at U11D-11. The input signal at

the data input signal was also all 1's or all 0's, the data

U11D-13 is B7 instead of B7. The output at U11D-11 is

randomizing function would not take place. The SETUP

the input at U11A-1. Column 5 shows the BFRD DATA

signal is used to avoid the possibility. At power turn-on,

input and column 6 shows the resulting output at U11A-3

the input at P1-13 supplies the +5 vdc Vcc operating

which is the input to the 15-stage shift register. When

voltage. This voltage is also applied through R12 to

the randomizer is inhibited, the scrambler feedback at

U8A-4, the PRE-SET input. Logic 0 is the active input

U11A-1 is not effective (open) and U11A-1 is grounded

signal level. The circuit wiring has capacitance to

causing the BFRD DATA to remain unchanged at U11A-

ground and this capacitance must charge to the logic 1

2 and U11A-3 when clocked into U8A-2.

level before a logic 1 is applied at U8A-4. During the

resultant delay time, U8A-4 has in effect a logic 0 input

(2) The descrambler circuit is similar to

and since it has operating Vcc applied, it is set, with

the scrambler circuit. The RCOVD DATA (P1-1) and

logic 1 at U8A-5. After the initial delay time, U8A-4 is

RCOVD TMG (P1-2) signals are applied to a 15-stage

logic 1 and the PRESET input is inactive. In a similar

shift register (U10, 6 stages; U2A, 1 stage; U7, 7 stages;

manner, the SETUP signal applies logic 0 at the CLE

and U2B, 1 stage) through buffers U15A and U15B.

input U1-9 during the delay time and the flip-flop in U1

The data input signal at U10-1 is clocked through the

are reset. Thus the SETUP signal prevents an initial

shift register. Bit B15 (U28-8) and B7 (U2A-5) through

state of all 1's or 0's in the shift register.

exclusive OR gate U15C control the logic action at

exclusive OR gate U15D. The input data signal (U15A-

(4) Monostable

retriggerable

multi-

3) is also applied to U15D and it is inverted or not by

vibrators (failure monitors) U9A, U9B and U5A are set at

U15D depending on the logic state of the signal at

power-up by pullup resistors R20 and R14. The failure

U15C-6. The truth table for the logic action that occurs

monitors have a timed output of 150 msec provided by

is the same as that given above for the scrambler,

external RC networks consisting of capacitors C4, C5

substituting U15C for U11D and U15D for U11A. The

and C6 and resistors R15, R16 and R17. When the

descrambled output signal at U15C-8 is then shifted

monitored input signal at U9A, U9B or U5A pins 1 or 9 is

through flip-flop U6A and buffer U13A to P1-M. When

active and

the randomizer is inhibited the feed forward bits at

U15D-9 are not effective and U150-9 is grounded

Change 6 2-16.8