The output (E24) of the delay circuit in the data pulse generator

TM 11-5820-695-35

negative. This condition holds and a negative pulse

the trigger input of narrow clock pulse generator A5

input to the integrator is generated until 1BP goes

which is a monostable multivibrator. It generates a

negative. When zero bits occur in the input signal

negative 120 nanosecond output pulse for each input

(1CSPCM), 1DP remains high and the phase

pulse. This signal is inverted by inverter A3A and

comparator flip-flop is not set, so 1FP remains high.

designated 1N2304 (2304 kHz cable-to-radio clock). It

Thus, 1PP remains low and positive pulses to the

is sent to cable digital processor lA12A4 and is also

integrator are not generated. Also 1BP remains low, so

connected to inverter A3D.

The output A3D is

1NP is high and negative pulses to the integrator are not

connected to both inputs of AND gate A2B, directly to

generated.

pin 6 and through delay inverters A2C, D and A to pin 5.

Because of the propagation delay through the three

(5) The output signal of differential integrator

inverters, the input signals to A2B are simultaneously

A8 is connected to the frequency control input of 4608

logic one only for a short time immediately following a

kHz vco 1A12A1. When the input to A8 is a positive

positive transition at the output of A3D (1CP waveform,

pulse, the output is a negative-going change in voltage.

fig. 5-31). The resulting logic zero output of A2B resets

When the input is a negative pulse, the output is a

phase comparator A10A and B. Tracing this action back

positive-going change in voltage. This means that the

to the input signal (1T4608), it can be seen that it occurs

output voltage starts to rise (or fall) at a fixed rate of

at the positive-going or leading edge of clock pulses.

change (slope).

When clock and data are in

The difference in time between set (1DP, data pulse)

synchronism, positive and negative pulse inputs to A8

and reset (1CP, clock pulse) pulses to the phase

are approximately equal, and the positive and negative-

comparator is then a measure of the phase difference

going changes in output voltage cancel since the slopes

between the data input, 1CSPCM and clock input,

are equal. These low amplitude excursions of the

1T4608.

output signal are filtered at the input of 1A12A1 and the

output frequency remains constant. When the positive

(3) The output (E24) of the delay circuit in the

pulses inputs to A8 are longer than the negative pulses,

data pulse generator ((1) above) is also connected to 48

the negative-going output caused by the positive pulse

channel baud generator A1 which is a monostable

is not entirely cancelled by the return in the zero

multivibrator. It generates a negative output pulse each

direction caused by the following negative pulse. The

time the input signal goes to logic zero. The duration of

net result is that the signal remains negative and will go

the negative pulse is adjusted so that the total time from

more negative as long as this condition (longer positive

the start to 1DP to the end of the baud pulse is 434

pulses) holds. However, the negative output signal

nanoseconds. This signal is inverted by inverter A3C

causes the frequency of 1A12A1 to increase, clock

and applied as one input (1BP) to AND gate A6A (1BP

pulse 1CP then occurs sooner and positive pulses are

waveform, fig. 5-31).

shortened and the length of negative pulses is

increased. This action and reaction occurs until positive

(4) The output signal of the phase comparator

and negative pulses are equal. When the negative

(1FP) (1FP waveform, fig. 5-31), which represents the

pulses are longer than positive pulses, the same kind of

phase difference between data and clock signals, is

action in the opposite direction takes place. The output

inverted by inverter A6B. The output signal of inverter

of A8 goes positive, clock frequency is decreased and

A6B (1PP waveform, fig. 5-31) causes the positive

clock pulses 1CP is delayed. This shortens the negative

pulse generator to generate the positive pulse input to

pulses. The result is that the output of A8 always

differential integrator AS. The inverter output of the 48

produces a frequency change at 1A12A1 that tends to

channel baud generator (1BP) and the output of the

equalize positive and negative pulses and when equality

phase comparator (1FP) are applied to AND gate A6A.

is established to maintain it. When the data signal has

The output of AND gate A6A (1NP waveform, fig. 5-31)

logic zero bits, neither positive nor negative pulses are

causes the negative pulse generator to generate the

sent to integrator A8, however, it has a long time

negative pulse input to differential integrator A8. Thus,

constant which holds its output to bridge over these

at the start of each data pulse (corresponding to a logic

short intervals.

one bit in the data signal) 1DP goes Negative, 1FP goes

negative, and 1PP goes positive. This condition holds

(6) The output of differential integrator A8 is

and a positive pulse input to the integrator is generated

also connected to positive/negative clamp detector A9.

until 1CP goes negative. When 1CP goes negative,

Normally, the output of differential

1FP goes positive and since 1BP is positive, 1NP goes

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