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TM 11-5820-695-35
(+5v) by A2D. The +5v applied to the base turns on
integrator A8 is close to zero volts as it holds the clock
transistor Q1, so the collector voltage is zero. Signal
signal in synchronism with data. The output of A9 is
1CCFAIL is logic 0 (normal) and lamp DS1 is lighted. If
then low. The low output from A9 is inverted twice by
either the traffic or the clock signal fails, the
the lamp driver (inverters A1OC and A4A), so signal
corresponding detector times out and its output goes to
1CCFAIL is low (logic zero) and lamp DS1 is lighted.
logic 0. The outputs of A2C and A2D are then logic 1
However, when correction is required, the output of A8
and logic 0, respectively Transistor Q1 is cut off, lamp
can vary from +3 volts to -3 volts. Positive/negative
DS1 turns off and the 1CCFAIL signal is logic 0 (alarm).
clamp detector A9 output signals of A8 that exceed the
This signal is routed to the alarm monitor 1A12A15.
indicated limits.  When either limit is exceeded the
output of A9 goes high. This signal, inverted twice by
c.  Cable Digital Processor lA12A4 (fig. 5-7 and 5-
the lamp driver, is sent to alarm monitor 1A12A5 and
also turns off lamp DS1.
32).
The cable-to-radio circuits of cable digital
processor 1A12A4 receive the inverted cable sliced pcm
b.1 Cable
Control
1A12A14,
signal (OCSPCM) from 1A12A3 (or 1A12A14) and
retime it, using cable-to-radio-clock signal (1N2304 or
Asynchronous Mode(fig.
5-7.1 and 5-31.1) In the
1NCLK) from 1A12A3 (or 1A12A14). The retimed pcm
asynchronous mode, the cable control comparator
signal levels are then converted to logic levels required
1A12A14 retimes the 1CSPCM signal and monitors the
by the radio modulator circuits.
pcm traffic signal and the clock signal.
(1)  The cable sliced pcm signal (OCSPCM) is
(1)  The traffic signal 1CSPCM is applied to the
applied to data retimer flip-flop A2A through inverter
D input of data retiming flip-flop A1A and the clock
A5A. The cable-to-radio clock signal is applied to data
signal 1CTIM is applied to the T input. Flip-flop A1A
retimer flip-flop A2A through digital buffer 1.  Data
triggers on the positive-going transitions of clock pulses.
retiming flip-flop A2A triggers on the positive-going
Each time A1A is triggered, the logic 0 output (pin 6)
transition of clock (trigger) pulses. Each time A2A is
takes on the logic state of the signal present at input D
triggered (waveform C, fig. 5-32), the logic one output
(pin 2).  Thus the half-baud input data pulses are
(pin 5) takes on the logic state of the signal present at
converted to full baud at the output of A1A. The output
input D (pin 2) at that, time. The logic state of output
data signal is precisely and uniformly retimed because
pin 6 is always the complement (logical opposite) of the
triggering of A1A is controlled by the clock signal
output at pin 5.  The output state of A2A is then
1CTIM. This signal, which is inverted since it is taken
maintained until the next trigger pulse. As a result, the
from the 0 output of A1A, is designated OCSPCM and is
half-baud data pulses at the D input (typical waveform
routed to cable digital processor 1A12A4.
B, fig. 5-32) are converted to full baud pulses at the
output (waveform D, fig. 5-32). The output signal of
(2)  The clock signal 1CTIM is inverted by clock
A2A is inverted since it is taken at the logic zero output
inverter A2A which also reshapes the clock pulses to
(pin 6). It is inverted again by inverter A4A (waveform
standard logic levels.  The output signal, designated
E, fig. 5-32), converted to voltage levels required by the
1NCLK is routed to cable digital regenerator 1A12A4.
modulator circuits and applied to the modulator circuits
of Transmitter, Radio T-1054/GRC-144.
(3)  The two output signals OCSPCM and
1NCLK are monitored by the traffic detector A3A and
(2)  The retimed pcm signal is also applied to
the clock detector A3B. The detector circuits are the
alarm circuit 1. Each time monstable multivibrator A6 is
same and their operation is the same. The circuit is a
triggered by the negative-going transition of a logic one
monostable multivibrator with an AND gate trigger input.
from A4A, the output signal (pin 8) goes to logic one and
Since the AND gate has one input (pins 1 and 9) tied
holds for 72 microseconds (approximately).  If A6
permanently to logic 1, triggering occurs regularly as
receives another trigger pulse before it times out (72
long as a traffic (or clock) signal is present. Each time
microseconds), the timing cycle starts over again. Thus,
the detector is triggered, the output (pins 13 and 5) goes
as long as pcm trigger pulses occur at least once every
to logic 1 and remains at logic 1 for a time determined
72 microseconds, the output of A6 is held at logic one.
by resistor R23 and capacitor C6 (or R6-C7). The time
The logic one ( +5v) keeps Q1 forward biased and it
is relatively long compared to the time between trigger
provides a logic zero output.  Lamp DS1 is lighted
inputs. So as long as the OCSPCM and 1NCLK signals
(green) and logic
are active, A3A and A3B present logic 1 inputs to A2C.
The output of A2C is logic 0; this is inverted to logic 1
Change 2 2-14


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