Cable Control Comparator 1A12A3

TM 11-5820-695-35

DS1 is off and signal 1CRFAIL is logic 1 (Alarm). When

filter (R8, R5, C6, C7) to the base of Q2 and is also

the pcm signal is active, the output of A2A goes

coupled through capacitor C10 to the base circuit of Q1.

negative (ground) between logic ones. During these

The base circuit of Q1 (CR2, R4, and C5) rectifies and

intervals (in effect, negative pulses), capacitor C32

filters the signal and provides, at the base of Q1, a dc

charges through CR9 from the positive +5v supply, with

signal which is proportional to the pcm signal amplitude.

negative polarity on the side connected to the base of

Diode CR3 bypasses the negative half-cycles of the

Q5. Transistor Q5 is turned on and the +6v supply

signal. Transistors Q1 and Q2 comprise a voltage

through resistor R36 and the emitter-collector circuit of

comparator with the reference voltage at the base of Q2

Q5 forward biases Q6. Transistor Q6 and lamp DS1 are

and the signal proportional voltage at the base of Q1.

turned on and signal 1CRFAIL is logic O (normal).

The signal at the base of Q2 is dc with the level

adjustable by variable resistor R5. The output voltage

(7) The output signal of A3 is also transformer

from the collector of Q1 is coupled through capacitors

coupled to limiter Amplifier A1 in the clock generator

C15 and C16 to linear amplifier A4. Resistor R17

circuit. The input circuit of the limiter amplifier is a

provides an impedance match for the output of A4.

crystal-controlled bandpass filter comprising the

secondary of transformer T2, crystal Y1, capacitors C18,

(5) The bipolar pcm signal is converted to

C19, and C23, resistor R20 and coil L9. The bandpass

standard logic (all logic ones are positive pulses) in the

filter provides a 4915. 2 kHz input to A1. The output of

dual voltage comparators of A3. The pcm signal in the

A1 is a signal of uniform amplitude at the clock

secondary of transformer T1 is connected through

frequency. Resistor R19 is the load resistor for A1; the

equalizing resistors (R30 and R33) to the noninverting

signal developed across R19 is capacitor-coupled (C11)

inputs of the voltage comparators. A bias voltage (+0.

to buffer amplifier Q3.

The output clock signal,

3 vdc), developed by resistor R18 and diode CR7, is

designated 1CTIM, is passed through inverter A2B and

connected through equalizing resistors (R31 and R32) to

routed to cable control comparator 1A12A14.

the Inverting inputs. The pcm input signal to A3 is

transformer coupled from A4, so the signals at pins 4

b. Cable Control Comparator 1A12A3 (fig. 5-7 and

and 6 are 180 degrees out of phase. When the signal at

pin 4 goes more positive than +0.3v (the signal on pin 6

5-31).

is then negative), the output of the comparator goes

positive and remains positive until the input signal falls

(1) The function of cable control comparator

below +0.3v.

Thus the positive bipolar pulse is

1A12A3 is to determine the phase difference between

converted to a squared pulse. When the signal at pin 4

the clock and data signals and from this information to

is negative (the negative bipolar pulse), the inverted

generate a control signal. The control signal is then

signal at pin 6 is positive. The same action as before

used to shift the phase of the clock signal until data and

now occurs in the voltage comparator connected to pin

clock are in phase. Cable control comparator 1A12A3

6, thus inverting and squaring the negative bipolar

receives the 1T4608 signal (4608 kHz cable-to-radio

pulse.

As the two voltage comparators operate

clock) from 4608 kHz vco 1A12A1 and the 1CSPCM

alternately to convert and square the bipolar pulses,

signal (cable sliced pcm) from cable digital regenerator

their outputs are combined in the OR-gate of A3 to

1A12A2. The 1CSPCM signal is inverted by inverter

provide the standard logic positive pulses in the same

A3B. The inverted signal (OCSPCM) is sent to cable

serial order as the original bipolar pulses. The output of

digital processor 1A12A4 and is also connected to the

A3 is sent through inverters A2C and A2A which provide

trigger input of flip-flop A7B which divides the signal by

the drive power for following circuits and reduce the

two. The output of A7B is connected to both inputs of

loading on A3.

The output of A2A, designated

AND gate A11B, directly to pin 6 and through delay

1CSPCM, is routed to cable control comparator

inverters A11C, D and A to pin 5 (E24). Because of the

1A12A14 and 4 to the integrator and lamp driver

propagation delay through the three inverters, the input

circuits.

signals to A11B are simultaneously logic one only for a

short time immediately following a positive transition at

(6) When the pcm signal is absent, the output

the output of flip-flop A7B (1DF waveform, fig. 5-31).

of A2A is high (+5v), the base circuit of transistor Q5

The resulting logic zero output of A11B sets phase

has +5v applied at both sides, capacitor C32 has no

comparator A10A and B. Tracing this action back to the

charge and +5 vdc through R35 is applied to the base of

input signal

Q5. With Q5 reverse biased and off, Q6 is off, lamp

Change 2 2-12.1