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| TM 11-5820-695-35
the pcm is sliced into separate voltage pulses, logic
work, variable in increments which provide attenuation
ones, which represent the logic one bits in the pcm code
equivalent to one-quarter mile of cable, is provided to
as shown in figure 2-2, waveform B The output of slicer
terminate the line. This consists of three one-quarter
A1 is zero for logic zero bits The dc voltage developed
mile sections which can be selected by the operator.
by peak detector Q7/Q8 assures that the center of each
The section or sections selected modify the input signals
voltage pulse corresponds to the peak of the pcm signal.
to an equivalent that would be delivered by one mile of
The pcm signal, now designated ICSPCM, is sent to
cable.
cable control comparator 1A12A3 for retiming.
(2) The original FRCX signal from the source
(5) The 1CSPCM signal is integrated by Q9
end of the cable is comprised of a dc signal plus
which develops a dc output signal as long as logic one
squared voltage pulses representing the one bits in the
bits keep occurring at the input Lamp driver Q10 then
pcm modulation code. When the orderwire circuit is in
provides a ground output and lamp DS1 lights to
use, the orderwire audio signal is the third component of
indicate traffic activity. In the absence of traffic, lamp
the FRCX signal. This signal, at the input to 1A12A2, is
DS1 does not light and signal 1CRFAIL, which goes to
greatly degraded in quality after transmission through
alarm monitor 1A12A5, switches to logic one.
one mile of cable (or equivalent). A typical input FRCX
signal is illustrated in figure 2-2, waveform A.
a.1. Cable
Digital
Regenerator
1A12A13,
(3) The pcm portion of the input signal is
coupled to the cable simulation networks and
transformer T1. Transformer T1 provides a voltage gain
(1) The discussion of the FRCX signal given in
of two. The dc is blocked from this path by capacitor C1
and the orderwire is rejected by highpass filter C1/L7.
asynchronous mode. The FRCX signal is illustrated in
Overvoltage protection for following amplifiers is
provided by diodes CR1-CR4 which limit the maximum
composite FRCX signal is passed by high pass filter
amplitude of the input signal The orderwire and dc
C12-L7 and the dc and orderwire components are routed
signals go through low pass filter L1, L2 and L3 and are
into a second path through low pass filter L-7, L-10, L-
sent to chassis mounted transformer 1A12A15AlT1 as
11, R-9 s and C-35. The dc/orderwire signal, designated
the FRCX∅W signal
FRCXOW, is sent to chassis mounted transformer
1A12A12A1T1.
(4) The pcm signal at the secondary of
(2) In the pcm signal path, overvoltage
transformer T1 is degraded because of high frequency
protection for following circuits is provided by diodes
losses during cable transmission The pcm voltage
CR5 and CR6. The signal then passes from terminal (T)
pulses are no longer clearly defined and square and are
to terminal (N), (passing through the variable cable
low in amplitude Circuit Q1, of the 2304 kHz peaking
equalizer via terminals (L) and (Y), if it is in the circuit),
circuit, amplifies the pcm voltage pulses to provide a
and goes through the fixed cable equalizer. Variable
more sharply defined signal In the 2304 kHz peaking
resistor R6 adjusts the low frequency response of the
circuit, circuit Q1 is tuned to 2304 kHz which is the
equalizer
frequency used to time pcm voltage pulses for cable
transmission. Circuit Q2, with a voltage gain of 35, then
(3) At this point the signal is coupled through
greatly increases the sharpness and definition of the
capacitor C22 to emitter follower Q4, the traffic monitor
pcm voltage pulses The output of circuit Q2 is coupled
amplifier The output of Q4, designated XCPCM, is
routed through a coaxial cable to alarm monitor
transformer T2 to amplifier Q5A Amplifier Q5A is a
1A12A15. Resistor R27 reduces the capacitive effect of
temperature compensated linear amplifier which further
the cable and prevents reflection of the signal back to
amplifies the signal Peak detector circuit A7/Q8 rectifies
Q4.
the pcm signal output of amplifier Q5A and develops a
filtered positive dc voltage across R40. The center arm
(4) An attenuator (resistors R12, R15 and R16)
of R40 is connected to the reference input of slicer Al.
at the input of linear amplifier A4 reduces the input
The pcm signal from Q5A also is connected to the other
signal to prevent overloading A4. The gain of linear
input of slicer A1. Slicer Al is a high speed differential
amplifier A4 is variable and is controlled by an agc
comparator. It produces a pulse output with a steep
signal developed in transistors Q1 and Q2 The output
vertical rise for positive voltage transitions of the input
signal of A4 Is coupled through a low pass
and a sharp vertical drop for negative transitions. Thus,
Change 2 2-12
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