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TM 11-5820-917-13
4-69. The basic microphage synthesizer phase-lock loop (figure 4-9) consists of
a voltage controlled oscillator (VCO) having a frequency range of 42 to 70 MHz, a
loop amplifier/integrator, a phase detector, and a counter/divider/comparator
string.  This basic synthesis loop is capable of synthesizing any frequency be-
tween 42 and 70 MHz in 100 kHz steps as determined by the effective divide ratio
in the divider between the VCO and the phase detector.  That is, for the VCO to
operate at 45.1 MHz, the divider must divide by 451 to achieve the required 100
kHz output for the phase detector.  (The phase detector reference is 100 kHz.)
Another way of considering this loop is to note that during the 10 microsecond
period of the phase detector reference, the VCO must advance exactly 451 cycles
(zero crossings ) if the loop is to lock properly.  To synthesize 45.15 MHz with
this loop would imply 451 1/2 cycles of phase every 10 microseconds. By adding
additional logic to the basic loop, the snythesizer can operate properly by pro-
cessing for the integer ( 451) and fractional (1/2) cycle of phase information. For
example, for the synthesizer to operate continuously at 42.123000 MHz, the phase
(i. e., VCO zero crossings) must advance 421 whole cycles plus 23/100 fractional
cycles every 10 microseconds.  A phase computer computes both the exact whole
number and fractional number of phase cycles of the programmed frequency
occurring in a 10 microsecond period.  The result of this phase computation is
then added to the stored phase value from the previous 10 microsecond frame.
For example, assume a continuous frequency of 42.123 MHz, and a phase register
initially at zero.  During the first 10 microsecond frame, the phase computer
calculates 421.23 cycles of phase.  For the second 1.0 microsecond frame, the
VCO advances another 421.23 + 421.23 = 842.46 total cycles by the end of the
second frame.  Similarly, for the third frame, The phase is advanced to 842.46 +
421.23 = 1263.69, and so on.
4-70. The synthesis loop operates by comparing and changing the VCO output
phase to equal that of the phase computer for both integer and fractional cycles.
Integer cycles (e.g., 421) of VCO phase are controlled by conventional phase-
lock loop techniques employing a high speed BCD counter and digital phase de-
tector.  The fractional remainder of VCO phase (e.g., 0.23) is handled by the
residue generator.  The residue generator is a digitally programmed waveform
generator, controlled by the phase computer, that corrects the output of the loop
phase detector for the remaining fractional cycle phase error occurring every
10 microseconds.  It is this programmed, fractional cycle, phase error correc-
tion capability that allows the loop to operate to a much finer frequency resolu-
tion than can normally be expected from a conventional (integer cycle) phase-lock
loop .  Thus, in this example, while the integer cycle BCD counter accumulates
an additional 421 cycles every 10 microseconds, the residue generator corrects
the phase detector by O, .23, .46, .69, etc. cycles every 10 microseconds to
produce a VCO output frequency of 42.123 MHz or 23 kHz offset from an integer
100 kHz point.  The ability of the residue generator to correct the loop is limited
only by the accuracy of the residue correction waveform.  In the sweep synthesizer
assembly, this correction is made with sufficient accuracy to provide 2 Hz frequency
resolution with spurious signals typically greater than 50 dB below the fundamental.
4-71.  SWEEP SYNTHESIZER (Part Number 5030-1101) (Refer to figures 4-10 and
4-11).  The sweep synthesizer 2A1 is a modular, digitally controlled, phase-locked-
loop synthesizer that generates the linear RF sweep.


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