CRT DISPLAY SECTION

TM 11-5820-917-13

NOTE

Decoder truncates (does not round off) frequencies at the 100 kHz decade.

4-32. CRT DISPLAY SECTION

4-33. DISPLAY SECTION DESCRIPTION. The CRT display section contains the

circuits that provide the RCS-4B with a bright, high resolution, digitally-

refreshed CRT display of chirp sounder record and receiver AGC voltage data.

This functional section contains three separate digital memories capable of stor-

ing three complete chirp sounder records; one for each path of the 3-path receiver

system. Each memory is organized to display 128 points for each vertical CRT

raster scan by 280 raster scan lines across the CRT. The CRT employs a high-

speed vertical raster (15 kHz) which requires 19.732 milliseconds to complete one

full picture of 280 lines plus 16 lines for the horizontal retrace. Timing control

within the CRT display circuits divides each memory into 280 segments, corre-

sponding to the 280 second sounder RF frequency sweep. Thus, each raster line

represents the data collected over one second of the receiver sweep. The data

acquired during one second of the RF sweep is processed by the spectrum

analyzer to provide propagation time delay information. Upon command of the

CRT display circuits, the spectrum analyzer outputs one spectral scan every

second, which corresponds to one vertical raster scan on the CRT display. The

spectrum analyzer outputs 200 data points during each spectrum scan which is

compressed to 100 points in the CRT display circuits. Thus, the CRT display

provides a 100 cell resolution of relative time delay data. In addition, the CRT

provides 28 points at the top of the vertical scan for receiver AGC bargraph infor-

mation. The total stored data displayed on the CRT is 128 x 280 = 35,840 bits.

All data is binary (on/off) with no gray scale information. The CRT digital

memories are continuously recirculated at high speeds (effective rate of 2.4 mega-

bits/second) to provide a flicker free display with an approximate 50-Hz refresh

rate. Due to timing limitations of the dynamic MOS shift registers used for the

memory, two parallel half size memories (called odd and even) are used. Thus

adjacent points along the 128-bit CRT vertical raster are stored alternately in the

even/odd memories (i. e. , bit positions O, 2, 4, 6. . . in the even memory and bits

1,3, 5,7... in the odd memory). These two memories are time multiplexed

such that the individual memories may be clocked at 1.2 MHz instead of 2.4 MHz.

All timing functions of the CRT display section are based on this 1.2 MHz memory

clock. Since the spectrum analyzer requires 60 milliseconds for its output scan,

temporary buffer registers are used which load the 100 bits (cells) of time delay

information from the spectrum analyzer (over a 60 millisecond period) and then

transfer this data at a 1.2 megabit rate into the main memories. Thus, while

each CRT raster line is equivalent to one spectrum analyzer output scan as far

as data content is concerned, the actual data rates are very different. The CRT

display system also provides six storable cursors which may be displayed over

any of the 280 CRT lines for ionogram reference information. The CRT is

annotated with frequency tick marks and numerical characters along the hori-

zontal axis which are generated by logic within the CRT display system.