RECEIVER CONTROL (cont)

TM 11-5820-917-13

4-30. The logic for the cursor to frequency conversion is represented in the

diagram of figure 4-6. This function is performed by cursor storage and readout

(1A2A1) and receiver control (1A4A1) circuits. Every 10-milliseconds, the start/

stop flip-flop U28 (figure FO-13/3) gates a clock derived from count divider U40

into BCD up-counters U20, U23, U24, and U27, which are started from count

0199. Each clock pulse advances the counter (U20) by one count of the "10 kHz"

decade of the LED display. This clock is also fed simultaneously to binary down-

counters (U43, U44, U45) on the cursor storage and readout circuit (1A2A1) which

contain a binary number representing the position (along the frequency axis) of

the cursor on the CRT display. The number ranges from zero (equivalent to

2.0 MHz) to 280 (equivalent to 30.0 MHz) corresponding to the 280 vertical raster

lines of the CRT frequency axis. Each raster line represents a 10 kHz wide seg-

ment of the receiver sweep. The binary down counter counts down from the cursor

location raster line number to zero while the BCD up counter simultaneously counts

up from 0199 (i.e. 1.99 MHz); each clock pulse advancing the count by 10 kHz.

When U45 "under-flows", a pulse (CUL) is generated which clears U28, thereby

stopping the up-down count sequence. Since the number of clock pulses for the

BCD up-counter is the same as for the binary down-counter, the total count

added to the BCD preset of 0199 provides the BCD equivalent of cursor frequency.

Note that there will always be at least one clock pulse to advance the BCD counter

from 0199 to 0200 even when the cursor is at line number "0" (at 2.00 MHz)

because the U45 borrow pulse (CUL) does not appear until the binary down

counter actually down counts past zero to minus one (- 1). At the end of ten milli-

seconds the two counters are cleared, the load enable activated, and the count

process repeated. The frequency of the moving cursor appears at the outputs

of BCD upcounters U20, U23, U24, and U27 every ten milliseconds. Actuating

the CURSOR FREQ switch connects the cursor BCD counters to the LED display

via the 16-pole switch (U21, U22, U25, U26) and latches U15 thru U18,

4-31. The preselector filter select circuit begins with three, 4-bit magnitude

comparators U10, U12, and U13, which compare the count frequency from the

frequency counter to the stored upper frequency limit of the filter passband

(figure FO-13/4). The filter cut-off frequencies are stored in a programmable-

read-only-memory, U11. U6, a 4-bit counter, is used to shift the PROM, U11,

through its address codes; each address corresponding to a preselector 1 thru

8. The PROM is shifted through all 16 address codes (only 8 are used) each time

the counter is updated, every 10 milliseconds. The PROM frequencies are arranged

from lowest frequency to highest. When a "less than flat" emerges from comparator

U13-7, U7-9 goes high latching the corresponding filter address code into U5.

U2 performs 1 out of 8 decoding. U9 and U4 are high voltage buffers, one of

whose outputs goes low (zero volts) when selecting the decoded preselector. The

eight preselector filters are selected as follows:

FREQUENCY RANGE

FILTER #

2.0- 2.9 MHz

3.0 - 4.3 MHz

4.4- 5.9 MHZ

6.0- 8.3 MHz

8.4 - 11.9 MHz

12.0 - 16.9 MHz

17.0 - 23.9 MHz

24.0 - 30.0 MHz

4-14