RECEIVER CONTROL

TM 11-5820-917-13

4-27. RECEIVER CONTROL (figure 4-5 and FO-13) (S/N 400101 and on). This

circuit performs various logic functions associated with the operation and control

of the RCS-4B. One, it provides a 100-kHz clock for each of the timers of the

3-path programmer with provision for slip synchronization; second, it counts

the VCO prescaled "count" signal from the synthesizer to drive the LED display

with the receive frequency of the receiver; third, it interfaces with the CRT

display logic to put the CRT cursor frequency on the LED display, when

requested; and last, it generates commands to automatically select the appropriate

preselector filters as the sweep progresses. The preselect filters are located in

the 4028 unit.

4-28. The 5-MHz standard enters on J1 and is connected to U51 and U52 (figure

FO-13/2) which forms a divide-by-50 yielding a 100 kHz square wave on U52-5.

U47, U46 and U39 are decade dividers which divide the 100 kHz to 5, 1, and

0.1 kHz. These three additional rates are used to modify, or "slip" the 100

kHz clocks sent to the timers by 5, 1, or 0.1 percent (fast, medium or slow).

The rates are identical to, and controlled by, the same means as the slip rate

dividers in the synthesizer. Speeding up or slowing down the basic 100 kHz

clock allows the synchronization timing to be advanced or retarded. Add pulses

at U35-6 and delete pulses at U35-8 are summed with the 100-kHz clock only

when the front panel MODE switch is in Set 1, Set 2, or Set 3 position, and the

ADV/RET switch is depressed to add/delete pulses to the selected timer only.

All the circuits that provide the 100-kHz clocks to the timers are powered

from the +5VB supply from the switching regulator 1A6A3. This supply has a

battery backup so timing synchronization is maintained during primary power

failure. Auto sync control pulses from the auto sync module are applied to

U35-4 and U35-10 to adjust the receiver timing during the auto sync timing

search.

4-29. The count signal (fo) that is input on J3 (figure FO-13/3) is related to

the receive frequency 1st L.O. as follows:

1st L.O. Frequency

The first L. O. frequency is related to the tune or receive frequency as follows:

L.O. Frequency = tune FREQ + 40.2 MHz

The count signal is processed by receiver control circuits to give an instan-

taneous readout of the receiver sweep frequency. This signal (f. = 2.11 MHz

to 3.51 MHz) is buffered by U31-10 and is fed to U40-6. U40 is a digital

counter programmed to divide-by-5. A gating control on U40-13 enables the

divider for 10-millisecond count intervals. The output of U 40 is sent to a four-

decade divide string, U29, U30, U32, and U33. At the conclusion of the 10-

millisecond period, the count in the counters is latched in output latches U15

through U8 whose outputs drive the LED display. Counter gating is provided

by a 100-HZ signal from the slip rate divider U39-12, which drives U19-1, a

divide-by- 2 circuit. The five inverters (U34, figure FO-13/4), which drive

U19-13, cause the 10-millisecond on, 10-millisecond off, gate output at U19-7 to

be slightly asymetical in time to avoid counter indecision when the synthesizer

is set to an integer frequency such as 2 MHz. (The 10-millisecond gate is on

approximately 20 nanoseconds longer than the 10-millisecond gate off time.)