ANALYZER INPUT SECTION

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high-speed recirculating memory is D-to-A converted and the resulting analog

waveform is a "time-compressed- frequency expanded" replica of the sampled input

waveform which repeats every memory recirculation time. The D-to-A output is then

fed to a heterodyne mixer whose local oscillator injection is a frequency sweep (from

a linear VCO) covering the entire bandwidth of the frequency-expanded signal

every 60 milliseconds. The output of the mixer is applied to a single, amplitude-

sampled filter that is synchronized to the 60-millisecond VCO frequency sweep and

the 300 microsecond memory recirculation. (The filter is sampled every 300 micro-

seconds.) The output of this filter is a series of voltage samples which represent

the amplitudes of the spectral components of the analyzed waveform. The resolution

of the analyzer is "200 lines", (200 memory recirculation every 60 milliseconds)

which is equivalent to dividing the analyzer input bandwidth (e.g. 500 Hz) in 200

parallel, frequency analysis filters. It is this high resolution spectral analysis which

gives the chirp sounding technique the ability to make clearly defined, highly sensi-

tive soundings with good "mode" or time delay, resolution. Functionally, the spectrum

analyzer consists of an input section, dealing with the digital processing (time com-

pression speedup) of the input signal, and an output section, covering the analog

swept filter analyzer.

4-12. ANALYZER INPUT SECTION (figures 4-2 and FO-9). The incoming signal

is first amplified and then sent to a sample-and-hold circuit whose sampling rate is

selected relative to the analysis range of interest. The analysis frequency range is

programmed by changing TTL programming lines and controlling the selection (U15)

of the sample rate divider. The two analysis ranges normally used by the sounder are

500 Hz and 5000 Hz, which require sample rates of 1500 and 15000 samples per second,

respectively. The sampling rate is always three times the highest input frequency of

interest. The normal analysis range for the receiver (except during auto sync) is

500 Hz. Analog samples of the input waveform taken by the sample and hold circuit

Q1 at the selected sampling frequency, are entered into an A-to-D converter

(figure FO-9/3) and translated into six-bit digital words. Flip-flops U1 and U3 are

used to latch the parallel output of the A/D converter before entering the data into

the memory load buffers. The clocking pulse for these flip-flops is the end-of-con-

version pulse (TP5) derived from the sampling circuit. The memory load buffers are

eight-bit shift registers whose digital bits are clocked forward by the buffer control

circuit (figure FO-9/4). The new data is clocked into the load buffers at the sampling

rate. The transfer of data from the buffer to the memory is keyed by the 2-MHz

memory clock but is also dependent on the status of the buffer control anti-coinci-

dence circuits. These circuits prevent coincidence problems between the loading

and unloading of the load buffer registers and insures that the contents of the

buffer are only clocked out following the "tail" of the circulating memory.

4-13. The memory (figure FO-9/5) is a 600 word, 6-bit per word, MOS shift

memory revolution). Two 2-MHz clock signals of different phase, derived from the

12-MHz oscillator (figure FO-9/1) continuously clock each of six parallel storage

registers which collectively circulate data words at a 2-MHz rate. Each of the six

parallel registers consists of three, serially connected, 200-bit long, MOS shift

registers to produce the required 600 word long memory. Each time a new input

sample is available from the load buffer, it is loaded in place of the oldest memory

sample following the "memory tail" (figure FO-9/4). This is achieved using a divide-

by-600 counter (U6, U7, and U8) which interfaces with shift register U29 to move

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