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TO 31R2-2GRC171-2
TM 11-5820-815-14
NAVELEX 0967-LP-544-5010
4-97. VOLTAGE REGULATOR. The voltage regulator
detector (figure FO-12) consists of two J-K flip-flops
(A2A7U1, A2A7Q1 of figure FO-19) develops regulated
(U3A, U3B), two NAND gates (U2C, U2B), and a cross-
+18 V dc from regulated +22 V dc. Amplifier A2A7U1
coupled NAND gate flip-flop (U2D, U2A). Under phase-
compares a reference voltage developed across zener
locked conditions, variable divider and reference divider
diode A2A7VR1 to a sample of the 18-V dc output
input pulses alternate with a certain phase difference
developed across voltage divider A2A7R3-R6-R7. The
between them. From the timing diagram of figure FO-12,
output of A2A7U1 provides base drive to turn on series
it can be observed that variable divider pulses (FV) set
pass transistor A2A7Q1.
Resistor A2A7R7 is test
the frequency/phase detector output (waveform C) to a
logic 1, and reference divider pulses (FR) set the output
selected to give about +18-V dc output voltage.
to a logic 0.  This produces an asymmetric output
waveform with duty cycle that represents the phase error
between the two input pulses.  Limiter amplifier Q2
inverts and limits the output waveform to specific logic
4-99.  Refer to the block diagram of figure FO-6 and
levels before applying it to the low-pass filter.  This
schematic diagram of figure FO-20 while reading the
eliminates amplitude variations in the frequency/phase
following circuit description. Unless otherwise specified,
detector output.  The low-pass filter filters the limiter
reference designators apply to components of receiver rf
amplifier output waveform to produce a dc tuning voltage
module A3.
to the vco.  The level of the dc tuning voltage is
proportional to the duty cycle of the waveform.
4-100. GENERAL. Receiver rf module A3 receives AM
rf signals from rf filter module A7 and provides detected
4-95. LOCK MONITOR. Reference designators apply to
audio to audio module A4. Refer to block diagram of
A2A7. The lock monitor (figure FO-12) consists of two J-
figure FO-6. The incoming receive rf signal (225.000 to
K flip-flops (U6A, U6B), a NOR gate (U20A), and a one-
399.975 MHz) is mixed with the receive injection signal
shot (U4A). From the timing diagram, it can be observed
(195.000 to 369.975 MHz) from the synthesizer to
that for phase-locked conditions, the J-inputs to flip-flops
produce the 30-MHz if signal. The if signal is filtered,
U6A and U6B are always logic 0 just prior to applications
amplified, and separated into two signal paths.  The
of pulses (FV and FR) to their clock inputs. As long as FV
upper signal path feeds the second mixer directly
through a filter/delay network and if amplifier. The lower
and FR pulses alternate, the true outputs (waveforms I
and J) of U6A and U6B remain at logic 0 and the p11
signal path feeds the noise channel if amplifier.  The
noise channel if amplifier processes impulse type noise
fault output of one-shot U4A remains at logic 1.
to turn off the 19.3-MHz oscillator signal to the second
4-96. When the frequency of the variable divider output
mixer whenever a pulse with certain characteristics is
detected.  The filter/delay network in the upper signal
becomes much greater or much less than the reference
path slows the noise pulse so that it arrives at the second
divider, the lock monitor indicates a p11 fault. From the
timing diagram it can be seen that if the variable divider
mixer during the time when the 19.3-MHz oscillator
signal is turned off. This circuit action mutes the receive
frequency becomes much greater than the reference
divider so that the reference divider (FR) and variable
rf so noise pulses do not appear at the output.
divider (FV) pulses no longer alternate, then the second
variable divider pulse causes the output of flip-flop U6A
4-101.  At the second mixer, the 30-MHz if signal is
to go to logic 1. The resulting negative transition at the
mixed with the 19.3-MHz oscillator signal to produce the
input to one-shot U4A causes the one-shot to generate a
10.7-MHz if signal. The 10.7-MHz if signal is filtered,
logic 0 output pulse (about 15 milliseconds wide) to
amplified, and applied to the detector where it is
indicate an out-of-lock condition. In a similar manner, if
demodulated into an audio signal superimposed on a dc
the variable divider frequency becomes much less than
level that is proportional to the average carrier level at
the reference divider, the output of flip-flop U6B goes to
the detector.  The audio is amplified and fed to the
logic 1 to produce a logic 0 p11 fault output from one-
receiver af output. The dc voltage is fed to the AGC
shot U4A. The one-shot is resettable such that each
circuit where it is integrated, amplified, and applied to if
negative transition at its inverting input resets the one-
amplifier and shunt attenuator circuits to control receive
shot to timeout for about 15 milliseconds. Keying the
gain.  The integrator provides the proper AGC time
transmitter generates a positive pulse at the non-
constant (attack and release times). AGC voltage is fed
inverting input to one-shot U4A. This results in a logic 0
to the squelch circuit on audio module A4 to provide
p11 fault output from U4A each time the transmitter is
receiver squelch control and to rf filter module A7 to
keyed.  The p11 fault output is applied to the keyer
provide front-end rf signal attenuation.
control circuit in audio module A4. When the transmitter
is keyed, the logic 0 p11 fault signal inhibits the key line
4-102. When the transmitter is keyed, the mute circuit
(key 2) to power amplifier A8 for about 15 milliseconds.
increases AGC voltage to force the rf receiver gain to
This allows the frequency synthesizer to stabilize at the
provide maximum attenuation to the receive rf signal.
transmit frequency before the power amplifier begins
This mutes the receiver.
transmitting the rf signal
TO 31R2-2GRC171-2
TM 11-5820-815-14

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