Np Programmable Counter

TO 31R2-2GRC171-2

TM 11-5820-815-14

NAVELEX 0967-LP-544-5010

4-88. Np Programmable Counter. The Np pro-

This is a result of the 30-MHz decoder(U26B, U19F).

grammable counter (figures FO-11 and FO-19) consists

The 30-MHz decoder decodes the QA, QB, and QC

of two programmable decade down counters (1-MHz

outputs of 10-MHz decade counter U11. After the 295th

decade counter U12 and 10-MHz decade counter U11),

clock pulse (T295), the outputs QA, QB, and QC of the

two J-K flip-flops connected as a 4-state up counter

10-MHz decade counter U11 (waveforms AE, AF, and

(100-MHz counter U10, U9). and an ANDed input J-K

AG) go to logic 1, logic 1, and logic 0 respectively. This

flip-flop (counter preset flip-flop U8) used as an end-of-

results in a logic 0 output from the 30-MHz decoder.

During receive mode, the logic 1 key 1 input enables

count decoder to generate the output pulses to the

frequency/phase detector. The 100-MHz counter is

gate U25A and allows the logic 0 output of the 30-MHz

programmed by 100-MHz frequency select information to

decoder to be applied through U25A and U25B to the

count from state 0 to state 3 for 300-MHz radio control

input of the counter preset logic. This causes waveform

frequencies and from state 1 to state 3 for 200-MHz

AP to go to logic 0 when the 30-MHz decoder output

frequencies. Through frequency select informa-tion, the

goes to logic 0 which occurs after the 295th clock pulse

Np programmable counter is preset to a count that

(T295). The other three inputs (waveforms AA, AC, and

AD) to the counter preset logic go to logic 0 when the

represents the transmit frequency. When the trans-

mitter is unkeyed, control logic reduces the count by 30

QA, QC, and QD outputs of 1-MHz decade counter U12

to cause a 30-MHz decrease in frequency. The following

go to logic 0. This occurs after 302 clock pulses (T302)

details the operation of the Np programmable counter

when the counter reaches state 2. The output (wave-

for the example frequency of 334.350 MHz. Refer to

form AR) goes to logic 1 to make the J-input to counter

figure FO-11 for a timing diagram.

preset flip-flop U8 logic 1.

4-89. Preset pulse W presets 1-MHz decade counter

4-92. With the J-input to counter preset flip-flop U8 at

U12 to counter state 4 and 10-MHz decade counter U11

logic 1, the next clock pulse (T333 for transmit mode, T303

for receive mode) to the Np programmable counter

to counter state 3. Preset pulses G and W preset 100-

MHz counter U10-U9 to counter state 0. This, in effect,

(inverted by U19C and applied to the clock input of U8)

presets the Np programmable counter to a count of 334.

causes U8 to change state. This generates the output

The process of counting input pulses (waveform Z) can

pulses (waveforms G and W) to the frequency/phase

detector which are also the reset pulses. The reset

be observed from the timing diagram. For the purpose

pulses reset the Np programmable counter causing the

of discussion, these pulses will be referred to as clock

J-input to counter preset flip-flop U8 to go to logic 0.

pulses.

With the J-input back to logic 0, the next input pulse to

the Np programmable counter causes counter preset

4-90. For both transmit and receive mode, the count

flip-flop U8 to revert back to its original state to start a

terminates two clock pulses after all inputs (waveforms

AK, AL, and AR) to the ANDed J-input of counter preset

new count period. Therefore, for transmit mode, the total

number of clock pulses counted by the Np

flip-flop U8 go to logic 1. Waveforms AK and AL from

the 100-MHz counter both go to logic 1 after the 235th

programmable counter is 334 which is equal to the

clock pulse (T235). Waveform AR from the counter

preset count for a frequency of 334.350 MHz. For

preset logic (U20C/D, U25C, and U21B) goes to logic 1

receive mode, the total number of clock pulses counted

when all inputs (waveforms AA, AC, AD, and AP) to the

is 304, which is 30 less than the preset count.

counter preset logic go to logic 0. This occurs as follows:

During transmit mode, the logic 0 key 1 input is inverted

4-93.

REFERENCE DIVIDER AND 3.2-MHz FRE-

by U19A and applied as logic 1 to gate U25D. This

QUENCY REFERENCE. The reference divider (figure

enables gate U25D and allows the BO output of 10-MHz

FO-19) consists of two bcd counters (A2A7U5, A2A7U7)

decade counter U11 to be applied through gates U25D

connected to divide by 256. The 3.2-MHz frequency

and U25B to the input of the counter preset logic. This

reference consists of a highly stable, temperature-

causes waveform AP to go to logic 0 when the BO output

controlled crystal oscillator (A2A8). By dividing the 3.2-

(waveform AN) of 10-MHz decade counter U11 goes to

MHz frequency reference output by 256, the reference

logic 0 which occurs after the 327th clock pulse (T327).

divider provides a highly stable 12.5-kHz signal to one-

The other three inputs (waveforms AA, AC, and AD) to

shot A2A7U4B. The one-shot generates both a logic 1

the counter preset logic go to logic 0 when the QA, QC,

and logic 0 output pulse at its output for each positive

and QD outputs of 1-MHz decade counter U12 go to

transition at its input. The RC time constant of resistor

logic 0. This occurs after the 332nd clock pulse (T332)

A2A7R13 and capacitor A2A7C7 determine the pulse

when the counter reaches state 2. With all inputs to the

width (about 100 microseconds). The logic 1 pulse is

counter preset logic at logic 0, the output (waveform AR)

applied to the frequency/phase detector reference input.

goes to logic 1 to make the J-input to counter preset flip-

Both pulses are applied to the lock monitor reference

flop U8 logic 1.

input.

4-91. During receive mode, waveform AR goes to logic

4-94.

FREQUENCY/PHASE DETECTOR, LIMITER

1, 30 clock pulses sooner than during transmit mode.

AMPLIFIER, AND LOW-PASS FILTER.

Reference

designators apply to A2A7. The frequency/phase

4-21