The impatt amplifier

TM 11-5820-695-35

from an input of +5 (positive) to a -5 (negative) output

the third harmonic of the input signal and isolated from,

voltage. The converter-regulator also has a turn-on

and coupled to the amplifier portion through circulator

protect circuit comprised of dual transistor Q1,

A1A1HY2. The amplifier portion of the frequency

associated bias resistors, capacitor C4 and relay K1.

multiplier is a series of tuned FET circuits comprising

The dual transistor and associated circuits protect the

Q2 and Q3 with tuned inputs and outputs. Transistors

frequency-amplifier 1A1A FET's, Q1 thru Q3, from burn-

Q2 and Q3 input and output filters (Z3, Z4 and Z5) are

out by making certain that the -5 V is applied to the

tuned to the third harmonic, is the load impedance, and

gates of Q1 thru Q3 prior to +5 V being applied to the

selects the third harmonic for each output. The output

drains. The +5 V keeps dual transistor Q1 turned off

signal from frequency multiplier 3A5A1 is set for an

which in turn keeps relay K1 deenergized until the dual

input signal level of +24 dBm at 31 RF IN when the

transistor Q1, biased by the -5 V, is turned on. When

output level feeding cable W2 is +12.5 dBm, minimum.

relay K1 is energized, +5 V is applied to frequency

All power to operate the frequency multiplier is supplied

tripler amplifier A1A1 circuits. The +5 V to -5 V turn on

by converter-regulator A1A2.

Converter-Regulator

delay is 5 msec minimum.

A1A2 is a +28 vdc to +5 vdc and -5 vdc regulated

converter that supplies bias voltages to frequency tripler

amplifier A1A1 circuits as follows:

b. The impatt amplifier is comprised of circulators

3A5HY1 through 3A5HY4 and associated circuits; it

CONV-REG

VOLTAGE

provides a total gain of 13.5 dB in three stages. The

TERMINAL

(DC)

first stage is a circulator coupled reflection amplifier

consisting of 3A5A2, 3A5HY1 and 3A5A3, with a gain of

4.65 to 5.05 V

5 dB (input 14.5 dBm, output 19.5 dBm). Bias "T" cavity

E4, E5

5.65 to 6.05 V

3A5A2 is a biasing and impedance matching circuit for

E6, E7

-0.5 to 0 V

impatt diode 3A5A3CR1 (refer to para c and d below for

(R2 or R9 max ccw)

the current regulator 3A5A8 functional description).

-3.3 to -5.3 V (R2 or R 9 max cw)

Ferrite circulator 3A5HY1 provides the RF transmission

-1.65 to -2.65 V

path to the following stage and also provides RF

5.65 to 6.05 V

isolation between the impatt diode and the driving

(Test Point)

source. Assembly 3A5A3 is a coaxial impatt diode

E10

-3.3 to -5.3 V

mounting circuit with coaxial matching circuit for

(Test Point)

regenerative amplification. Impatt diode 3A5A3CR1 is a

high efficiency (10%) silicon drift device with low

The converter-regulator is powered from the converter-

thermal resistance (10 C/W). The output signal from

multiplier power supply 3A6 (fig. 5-103). See figure

the first stage is coupled to the second stage through

5.102-2. Voltage regulator VR1 is a linear +5 V, 1.OA

isolating circulator 3A5HY2. The 50 ohm load 3A5AT3

regulator whose internal circuits contain short circuit and

is a termination for port 3 of 3A5HY2. The second stage

thermal shut down protective elements. Thermal shut

amplifier, 3A5HY3, 3A5A4 and 3A5A5 provides a gain

down occurs whenever VR1 junction temperature is in

of 4.5 dB (19.5 dBm input, 24 dBm output). It is similar

excess of 150 C, Regulated +5 vdc is applied to

in operation to stage 1. The

frequency tripler-amplifier A1A1 circuits through relay

K1 and to CMOS voltage converter lU1. The CMOS

voltage converter performs supply voltage conversion

Change 6 2-136