The registers in 1A14A5

TM 11-5820-695-35

are inverted in their associated gates and set the state

is equal to 20 periods of the incoming clock pulses (40

of associated flip-flops; for this example, the count

periods of the if output frequency from 1A14A2). The

becomes 01010101. The next incoming clock pulse will

repetition rate of the count signal at Z14C-8 is equal to

reset control flip-flop Z7 and remove the inhibit signal on

100 periods of the clock pulses (200 periods of the if

gate Z4B. Starting with the next clock pulse from Z2B,

output frequency from 1A14A2). The time from T, to

stage Z6 will start counting down. This operation

T,, is the width of the count pulse applied to variable

continues until all the register stages again reach zero.

frequency divider 1A14A6. Z18 pin 11 provides the

output reset signal which is used in 1A14A5 to control

the width.

f. The tart of the count down for stage Z6 can be

delayed by one clock period depending upon the setting

e. The registers in 1A14A5 contain the most

of the least significant bit (1) of the 0.,1 MHz switch.

significant bits and will reach their unique number before

The timing associated with this operation is shown in

the registers in 1A14A4 have reached their unique

figure 2-19. As Z611 goes to a logic one state at time

number. When the registers in 1A14A5 count down to

35, it raises Z3B-10 to logic one forcing Z5-4 to a logic

the two most significant digits of the unique number, the

zero. This conditions Z5 to be set on the next clock

reset enable signal is decoded in 1A14A5 and is applied

pulse. Therefore, the next clock pulse (time 36) from

to 1A14A4. The reset enable signal is applied as a low

Z2B-6 sets Z5-3 to a one. Since Z5-11 is zero, Z4B-4 is

(0-volt) level to NAND gate Z14A in 1A14A4. It is

also zero. For this condition, stage Z6 is stopped from

inverted to high (-volt) level and applied as one input to

counting and Z-8 remains a logic one. Z74-3 is forced

NAND gates Z3A and Z3B. At time R85 (fig. 2-18(2))

to a one on the next clock pulse. This places a one on

the count in registers Z18 (most significant bit), Z17,

Z4C-9. The next clock pulse from Z2B-6 raises Z-11l to

Z16, Z18, Z12, Z10, Z8, and Z6 (least significant) bit is

a one causing Z4B-4 to also be a logic one. This

011100100. Since control gate Z3 has been provided

imposes the following levels on Z4C; pin 10 is one, pin 9

by the reset enable signal from 1A14A5, this count,

is one. The output at Z4C-8 now depends on whether a

which is the unique number (decimal 64), will be

one or a zero condition is programmed in on Z4C-11-1

decoded by gates Z3A, Z3B and provide a logic zero

from the least significant bit (1) from the 0.1 MHz

level to Sea-. The following positive going transition

thumbwheel switch. If a logic one is programmed in,

from Z1-11 will set Z5, causing gate Z2A to produce a

Z4C-8 will go -to a zero allowing Z6-3 to switch off (logic

zero level initialize signal. The initialize signal sets all

zero) at the next clock pulse. If a zero is programmed

in, Z4C-8 will go to a one, thereby keeping Z6-3 at a

next count applied to Z6 by Z2B is inhibited by the one

high level when the next clock pulse occurs, and not

level applied to pin ten of Z6 by the output of NAND

changing state until the following clock pulse (T,). The

gate Z4B. However, the count transition from Z2B is

effect of the delay is to change the total count by the

applied to flip-flop Z7 which sets it. The inhibit signal

addition of two counts.

becomes a zero level that is applied to pin 3 of NAND-

gate Z4B. The next count transition applied to Z6 from

g. The count output pulses at output pin 11 of flip-

gate Z2B is, therefore, also inhibited, but it resets flip-

flop Z18 are monitored by a lamp bias circuit. A

flop Z5 and produces a zero level output from NAND

negative voltage is developed at the base of the

gate Z2C which is inverted by gate Z2D to produce a

transistor in lamp assembly DS1 by diodes CR2 and

one level preload signal. The preload signal is applied

CR8 which keeps the transistor nonconducting and the

to the switch gates in this module and in 1A14A6

failure lamp extinguished. The negative bias voltage is

causing the thumbwheel switch settings to be gated into

produced by capacitor C11 discharging through diode

the registers. This is illustrated in figure 2-18(2), where

CR8 and charging capacitor C12 in a negative direction

the assumption is made that the 1 MHz and 0.1 MHz

with respect to ground (+5V RET). If the count signal is

thumbwheel switch sections on the main chassis are

not present, the base of the transistor in lamp assembly

each set at position 5. With the switches in this position,

DS1 becomes positive through resistor R12 and the

the 4 and 1 inputs to the switch gates Z9B, Z16B and

transistor conducts, lighting the failure indicator lamp

Z4C, Z9D are a zero level (grounded through the switch

DS1

red.

sections). The 8 and 2 inputs are not TM 11-5820-6955

grounded and are a one level (5 volt); these input levels

2-101