Variable 1 Frequency Divider 1A14A4 Circuit Functioning

TM 11-5820-695-35

test by selecting the value of resistor R32. The nominal

the voltage across CR4 and R13 to be further reduced.

value of resistor R32 is 470k ohms.

The lowest voltage is developed across CR4 and R13

when both Q8 and Q9 are conducting (2 and 2are both

c. The sawtooth waveform at the output of buffer

a one level); then, the only path for current is through

Q5 and Q6 produces a bias for lamp DS1. The positive

R14. Since R16 is twice R15, the voltage charge with

sawtooth signal keeps ac detector Q1 conducting which

Q9 conducting is half the voltage change when Q8

keeps the transistor in the DS1 assembly

conducts. The correction code can be 00, 01, 10 or 11;

nonconducting. If the sawtooth signal is not present the

a logic zero corresponds to zero volt (transistor

base of ac detector Q1 becomes zero and is turned off.

nonconducting;) a logic one corresponds to 5 volts

This will cause the transistor in assembly DS1 to

(transistor conducting).

The maximum, sawtooth

conduct and light the failure indicator DS1 lamp red.

starting voltage corresponds to an input code of 00; it

Pressing the TEST pushbutton on the main chassis

gets progressively lower from 01 to 10 and is minimum

applies a 5-volt lamp test signal to pin P1-8, to terminal

for code 11. Varying the starting voltage of the

El through resistor R3, and to the base of the transistor

sawtooth waveform step changes the vco bias voltage.

in DS1 which lights the lamp.

The vco bias voltage is applied to the radio frequency

oscillator 1A14A1. This results in a faster return to the

d. Diodes CR2 and CR10 and transistor Q2 form a

phase locked condition or faster frequency capture. The

voltage regulator which converts the 28 volt input to 20

voltage developed across C8 and C9 is applied to the

volts. Only the transistors in the lamp circuits operate

input of buffer stage Q5 and Q6 which buffer the step

directly from the 28-volt supply in order to isolate the

level and sawtooth to the input of the sample and hold

vco bias voltage from any spurious variations.

circuit.

2-60. Variable 1 Frequency Divider 1A14A4 Circuit

b. The sample and hold circuit consists of

Functioning (fig. 5-0)

transistor Q7, which gates the composite signal, and

capacitor C14, which stores (or holds) the gated voltage

NOTE

level. Transistor .Q7 is a dual emitter gate which has a

low resistance bi-directional conduction path between

Variable 1 frequency divider 1A14A4

the two emitters when a positive voltage is applied

contains

integrated

circuits

between the collector and base. The gate is opened by

designated

through

Z18.

the divide-by-N pulses which are applied through pins

Integrated circuit types M(C932, 949,

P1-13 and P1-14, terminals Ell and E12, and resistor

950, 983, 9002, and MSC6847L are

R19 to transformer T2. Diode CR8 prevents spurious

used.

These circuits are shown

signals from being applied to T2. During normal phase-

functionally in figure 5-0. A circuit

locked operation, the divide-by-N and the 1.5625 kHz

diagram for each of these circuits is

reference are both the same frequency; therefore. the

provided in figure 5-24.

gate will open at the same ramp point of the sawtooth,

thus keeping the charge on C14 constant and the vco

bias voltage steady.

Capacitor C14 charges or

a. Variable 1 frequency divider 1A14A4 contains

discharges through Q7 to the incoming sawtooth voltage

two printed wiring boards All and A2 which provide the

while the gate is open and stores the voltage.

following circuits: clamp circuit CR1, driver Q1, divide-

Transistors Q10 and Q11 are a unity gain buffer

by-two circuit Z1, two 0.1 MHz and 1 MHz cascaded

amplifier and Q18 and Q18 act as complementary pair

divide-by-ten counter registers, control flip-flops and

dc amplifier. The resulting vco bias voltage is filtered by

gates. The if output frequency from 1A14A2 is applied

the network consisting of resistors R28 through R31

to divide-by-two Z1, through clamp circuit diode CR1

capacitors C12, C18, C16, and C17. This network is a

and driver Q1. The output from terminal 11 of divide-

parallel-Tee filter with maximum rejection at 1.5625 kHz

by-two circuit Z1 is applied to input inverter Z2 with the

The output is coupled to radio frequency oscillator

final inverted output from Z2 applied to the first stage

1A14A1 through terminals E14 and E16 and coaxial

(Z6) of the divide by-ten counter registers. The output

connector P1-A1. The range of dc control is set at final

pulsed from input inverter 72B are the clock pulses for

the cascaded divide-by-ten counter registers.

The

2-97