Fixed Frequency Divider 1A14A6 Block Diagram Description

TM 11-5820-695-35

frequency divider 1A14A6 generates a phase-lock alarm

(a)

The count down-cycle continues until all

signal and produces the two-bit correction codes for the

of the registers Z2 through Z9 contain zeros. The next

audio frequency phase error detector 1A14A3.

count pulse triggers the divide-by-eight ripple-through

counter registers Z7, Z8, and Z9 which sets the output

(2) The 8.0 MHz sinusoidal signal from

standard radio frequency oscillator 1A14A7 is applied to

this time one of the 10 MHz registers conditions the

board A2. The 8.0 MHz signal is changed by clamp

output register Z10 to be reset. After 40 cycles of the if

diode CR1 and inverted through inverter Z15 and

output frequency signal have been counted in variable 1

applied to divider stages Z1 through Z10 and Z11

frequency divider 1A14A4 an output reset signal is sent

through Z13. These stages divide the 8 MHz signal by

to reset output register Z10 which terminates the divide-

5120 to provide the 1.5625 kHz reference signal. The

by-N pulse. At the unique count (decimal 74, 1 + 536

1.5625 kHz reference signal is applied to audio

count), the registers in 1A14A5 are in the required

frequency phase error detector 1A14A3 through output

condition to satisfy the conditions for the reset enable

The 1.5625 kHz

gate Z1 and a reset enable level is applied to variable 1

reference signal is also applied to fixed frequency

frequency divider 1A14A4. When the registers in

divider board A1 through output register Z14. The

variable 1 frequency divider No. 1 1A14A4 are at their

1.5625 kHz output from divider Z13 is monitored by

unique count (decimal 64, 1 + 536 count), control flip-

failure lamp DS1 through bias diode CR3 and lamp

flops Z5 and Z7 on 1A14A4 are triggered to produce the

driver Q1. For normal conditions, lamp driver Q1 is

inhibit, initialize, and preload signals (537 + 3 count).

turned on and a transistor in the lamp assembly is

The inhibit level is applied to the 10 MHz counter

turned off causing failure lamp DS1 to be extinguished.

When the 1.5625 kHz output from divider Z.1S is not

initialize pulse is applied to the registers in variable 2

present, lamp driver Q1 turns off and the transistor in

frequency divider and they are set to a count which

the lamp assembly turns on causing failure lamp DS1 to

enables the registers to be modified by the thumbwheel

light red. Pressing the TEST button on electrical

switch settings. The preload pulse is applied to all the

frequency synthesizer 1A114 front panel applies 5 vdc

to the lamp transistor driver causing the failure lamp to

switch gates to open. With the switch gates Z12 through

light red.

Z14 opened, the thumbwheel switch settings modify the

count in the registers. The preloaded registers then

(3) The divide-by-N signal from variable 2

count down during the next count-down cycle.

frequency divider 1A14A5 is also applied to board A1 of

1A14A6 where it is compared with the 1.5625 kHz

(b)

The divide-by-N signal is monitored by

reference signal in the phase-lock detector circuits Z16

lamp driver Q1 and if it is not within the required

through Z18. If the signals are in phase, the phase-lock

amplitude and frequency limits, the lamp bias changes

detector circuits are balanced.

For this condition

and failure lamp DS1 lights red. Pressing the TEST

(phase-loop locked), the output of the phase-lock

button on the frequency synthesizer 1A14 front panel

detector circuits is unchanged and no signals are

applies 5 volts dc directly to the lamp transistor driver

applied to inverter Z24. The output of inverter Z24 is

circuit causing the failure lamp DS1 to light red. For

applied through alarm bias diode CR1 to the failure

normal operating conditions the failure lamp DS1 is

lamp DS1 assembly and to alarm driver Q2. With no

extinguished.

signals applied to inverter Z24, failure lamp M1 is

extinguished (normal condition) and alarm driver Q2 is

Fixed Frequency Divider 1A14A6 Block

turned off. The output from alarm driver Q2 is applied

Diagram Description (fig. 5-13).

through main chassis low pass filter 1A14FL3 (synth

lock) to the SYNTH LOCK indicator on meter panel

(1) Fixed frequency divider 1A14A6 contains

assembly 1A15A8. With alarm driver Q2 turned off, the

two printed circuit boards A1 and A2 that perform three

SYNTH LOCK indicator lights green (normal indication).

functions: (1) the 8.0 MHz signal from the standard

If the divide-by-N pulses and the 1.6625 kHz signals are

radio frequency oscillator 1AI14A7 is divided by 5120 to

not in phase, the phase-lock detector circuits become

produce the 1.5625 kHz reference signal, (2) the 1.5625

unbalanced and squarewave pulses are applied

kHz reference signal and the divide-by-N ( ) signal

from variable 2 frequency divider 1A14A5 are

compared, and (3) if the signals are not in phase, fixed

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