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TM 11-5820-695-35
is logic 1 U8 then has no effect and U12A operates
normally.
In  analog  orderwire  mode,  signal
passed through a low pass filter (R28, C26, C27, CR4
AVOW/DVOW is logic 1 and U8-10 applies a constant.
with cutoff frequency approximately 1 Hz) and applied to
logic 0 at U12A-2. With no input signal activity, U12A
X180 amplifier U7A. The output of U7A is a dc signal
times out and resets, but the constant logic 1 at U11C-9
proportional to the residual data component in the signal
holds the output U11C-10 at logic 0. This prevents a
from U4A-12. The output at U7A-12 is applied through
CVDOW fail indication in analog orderwire mode, since
a coupling network (R19, R21, C19) to LPF U7B
then there is no CVDOW signal. Nor gate U11A can still
(identical to LPF U4B, (4) above).  The regenerated
process the monitor signal from U12B normally.  For
data signal (7U88-4) is also coupled at this point. The
digital orderwire mode, with normal activity of monitored
AGC voltage from U7A regulates the level of the input
signals, U12A and B are set. U11C then has logic 0 at
signal to LPF U7B.  The filtered and AGC level-
pin 9 and logic 1 at pin 8. UllC-10 applies logic 0 at
controlled data only signal output of LPF U7B is finally
UllA-2 and U128-12 applies logic 0 at U11A-3. UllA-1 is
the required second input to subtractor U4A.  The
then logic 1 and UllB-4 and status signal SLICER FAIL
feedback signal from the subtractor output (U4A-12) into
are both logic 0 (normal). This signal inverted in U8D
the servo loop at U5-1 provides for maximum
holds indicator CR7 off. This condition is shown in the
cancellation of the data component. The output signal
first line of the chart on the following page for DGTL
at U4A-12 is then the required "clean" orderwire signal.
position. The chart shows the logic states of the monitor
The signal at U8E-12 is normally high (logic 1) and U8E
circuits for normal and fail conditions and for both
is isolated from the servo loop ((8) below).
positions of the OW SEL switch.
(6) In digital orderwire mode, the output
(8) Differential amplifier U2 and voltage
signal at U4A-12 is the CVDOW signal; in analog
comparator U3 monitor the from radio signal activity and
orderwire mode it is the AVOW signal. The CVDOW
generate status signal FR FAIL (P1-2).  The peak
signal is applied through R54 to CVDOW slicer U3A at
tracking signals from U6 are applied to differential
pin 3 and through a low pass filter (cutoff frequency 10
amplifier U2. The output signal at U2-6 is the voltage
Hz) at U3A-4.  In U3A the CVDOW signal is center
difference between positive and negative peaks.  As
sliced and the regenerated CVDOW output signal is
explained in (2) above. this voltage is a maximum 2.6
routed (Pl-l) to module A6.  In orderwire mode, the
V.  It varies with the from radio signal but is always
unfiltered AVOW signal output at U4A-12 is routed (P1-
present as long as the from radio signal is active. A
3) to module A6.
reference voltage derived front +5 vdc through R7, R8
(7) Status
monitor
monostable
U12B
and R9 is applied to voltage comparator U3 at pin 11. It
monitors activity of the SLICED DATA signal (U10-13)
is set to a level of +1 Vdc by adjustment of R8. as long
and U12A monitors activity of the SLICED CVDOW
as the voltage at U3-12 is more positive than the
signal (U3A-15).  As long as monitored signals are
voltage at U3-11, the output signal at U3-8 is ground
active, U12A and B are held in the set state with logic 1
(logic 0). Signal FR FAIL is then logic 0 (normal) and
at U12B-5 and U12A-13.  OW SEL switch 1A12S1
the output at U8E-12 is logic 1 ((5) above). If from radio
applies a control signal (Pl-10) through inverter U8 to
signal activity fails, the output signal at U3-8 changes to
CVDOW monitor U12A.  In digital orderwire mode,
high impedance and +5 Vdc through pull-up
signal AVOW/DVOW is logic 0 and the signal at U8-10
Change 6 2-24.14


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