Digital Regenerator 1A12A8

TM 11-5820-695-35

signal is routed to module A5; the orderwire signal is

routed to module A6. The retimed, regenerated data

(9) The DVDOW signal is applied to pin 12 of

signal is returned from A5 to A8 and used in the

DOW demultiplexer U7 and the 2 kHz signal is applied

separation of the orderwire signal from the data signal.

at pin 11. The redundant DOW bits in the CVDOW

Status signals SLICER FAIL and FR FAIL are routed to

signal start with logic 0 for DOW logic 0 and with logic 1

module A2.

for DOW logic 1 ((1)(c) above). U7 transfers the logic

(1) The composite data/OW signal is applied

state of the signal at pin 12 to pin 9 only at the rising

to X4 amplifier U9. Resistor R39 is a line termination

edge of the clock signal at pin 11. Since the 2 kHz

and R40 is used to adjust the input level to U9 to obtain

signal is synchronized to DOW transitions ((8) above)

a level of 4 volts peak-to-peak at the output. The

this means that only the first bit in the redundant DOW

amplified composite data/OW signal must be processed

signal is passed through U7. Thus, the correct DOW bit

to separate the data and orderwire signals. The output

values are demultiplexed.

at U9-11 is connected to U6 and U10 for data separation

(10) The DVOW data and, timing signals are

((2) below) and to low pass filter (LPF), U4B or orderwire

converted to balanced signals in line driver U9.

separation ((5) below). Output signals are taken from

Resistors R1 through R5, C3 and CR1 balance the

U6 or from radio signal activity monitoring ((8) below).

signals to ground. The DOW data and timing signals

(2) U6 and associated circuitry comprise a

are similarly processed in U8. The output signals are

peak-to-peak tracking threshold circuit. One transistor

routed to the OCU. The signal at Pl-17 is from OW SEL

in U6 has +12 V applied at the collector (U6-1) through

switch lA12Sl. In digital mode, this signal is logic 0 and

R46. The other transistor has -12 V applied at the

the signal at U13-2 enables U8, U9 and U12. Thus for

collector (U6-7) through R48.

The composite

digital mode, module A7 is operational. In analog

data/orderwire signal from U9-11 is applied at U6-2 and

orderwire mode, the signal at Pl-17 is logic 1. Logic 0

U6-6. The peak-to-peak values of this signal vary with

from U13-2 then inhibits all data and timing signal

changes in the data and the orderwire signal

outputs and prevents an alarm indication.

components. Thus its average value also varies. To

(11) The DVOW data and timing signals are

slice the signal precisely at data signal transitions, it is

applied to monitor U11. As long as both signals are

necessary to determine the average (transition) level.

active, Ull-5 applies logic 1 at U12-3. Similarly as long

As the signal varies between positive and negative

as the CVDOW and the 2 kHz (DOW) timing signals are

values, the transistors in U6 are alternately turned on.

active, Ull-13 applies logic 1 at U12-5. U12-6 then

When the signal is positive, base U6-2 is forward biased

applies logic 0 at U12-13. The resulting logic 1 at U12-

and capacitor C48 is charged from ground through C48,

12 is inverted in U13 and the OWDMX FAIL signal is

U6-3, U6-1, and R46. When the signal is negative, base

logic 0 (normal). This signal, inverted at U13-12 holds

U6-6 is forward biased and C47 charged from -12 V

status indicator CR off. If any data or timing signal fails

through R48, U6-7, U6-5 and C47 to ground. The

these conditions are reversed.

voltages developed across the capacitors are of

f. Digital Regenerator 1A12A8 (fig. 5-8.3 and 5-

opposite polarities and they track the varying negative

38.10).

Digital regenerator lA12A8 receives the

(C47) and

composite data/OW signal from the radio (P1-17) and

separates the data and orderwire signals. The data

Change 6 2-24.12