Digital Interface Buffer 1A12A4 - TM-11-5820-695-350088

TM 11-5820-695-35

signals from DATA RATE SEL (MB) switch 1A12S4 are

used to set the operating data rate of module A5.

(4) Inputs at U2D are both normally logic 0

(1) One of four external crystals (Y1 through

and U2D-ll is logic 1. The signal at U2D-ll can go to

Y4) is used to set the operating frequency of oscillator

logic 0 only when EQPT FAIL signal is logic 1 (fault)

U18.

The selected crystal is connected into the

while LOOP TEST switch 1A12S3 is not in DGM

oscillator circuit when the corresponding control diode

position. Similarly the signal at U2A-3 is logic O only

(CR1/Yl, CR2/Y2, CR3/Y3 or CR4/Y4) is forward biased.

when FR FAIL is logic 1 (fault) while S3 is not in DGM

Circuit operation for selection of crystal Y1 is typical.

position. These two signals with the signal from U11C

When the signal at U2A-2 is logic 1 (crystal Y1 not

((2) above) are inputs to U8B. Normally U8B has three

selected), +12 vdc through R1, R6 and L1 is applied to

logic 1 inputs and U88-6 is logic 0. Signal ORTFL is

the anode of CR1. U2 is an open collector type IC, and

then logic 1 and signal IRTFL is logic 0. These signals

the logic 1 at U2A-2 is a high impedance. With a high

are routed through P1-17 and -18 to external traffic

impedance at the junction of R2 and R7, the +12 vdc is

alarm locations. If any input at U8B changes to logic 0

also applied through R2, R7, L2 and L3 to the cathode

(fault), U8B-6 changes to logic 1 and ORTFL and

of CR1. CR1 is reverse biased and crystal Y1 is

1RTFL reverse logic states. The signal from U8B-6,

isolated from the oscillator circuit. When the signal at

inverted in U11F, is routed to P1-12 (TFC OUT) and is

U2A-2 switches to logic 0 ((5) below), the junction of R2

used for test purposes only.

and R7 is grounded. Now diode CR1 is forward biased

b. Digital Interface Buffer 1A12A4 ( fig. 5-8.3 and

with the cathode connected to ground through L3, L2

5-38.6). Digital buffer interface }A12A4 receives the

and R7 but with the anode still connected to +12 vdc.

retimed, radio recovered descrambled data signal ,from

CR1 then provides a low impedance path between C8

module A3. In A4 this signal is routed to the DGM

and L7 and crystal Y1 is connected into the oscillator

normally. When in radio loopback mode, it is returned

circuit through C7 and C8. Variable inductor L7 is a

to the remote site by radio. Operation of the circuits of

trimmer used to fine tune the oscillator frequency.

A4 for these functions is explained in paragraph 2.5.1d.

Inductors L1, L2, and L3 isolate the dc control circuit of

c. Digital Traffic Retimer 1A12A5 (fig. 5-8.3 and

CR1 from the oscillator circuit. Crystals Y2, Y3, and Y4

5.38-7. The function of digital traffic retimer 1A12A5 is

are isolated by their control diodes when crystal Y1 is

to retime the SLICED DATA signal received from

selected. These crystals are selected in a similar

module A8 at P1-2 and -3. The retimed data output

manner when U2B, U2C, or U2D is switched to logic 0

signal (RCOVD DATA, P1-M) and the data clock signal

by the crystal select logic circuits.

(RCOVD TMG, Pl-12) are routed to module A4. The

(2) The frequency of oscillator U18, operating

retimed data signal (REG DATA, Pl-10) is also routed to

with selected crystal, is phase controlled by varactor

module A8. The data clock signal is synchronized to the

diode CR5. The capacitance of CR5 is controlled by a

timing of the input data signal transitions in a phase lock

dc signal generated by the phase lock loop and applied

loop. The phase lock loop and retimed data signals are

at the anode. The

monitored to generate a status signal. The status signal

(DRPLL FAIL, P1-L) is routed to module A2. Input

Change 6 2-24.3