Signals DATA and TMG

TM 11-5820-695-35

(2) Multiplexer U7 is a quadruple 2-pole

with the retimed data signal. Input signals are: 1) data

electronic switch; switching operation is controlled by the

and timing signals from the DGM; 2) radio recovered

B/A input at pin 1. Logic 1 levels for the signal inputs to

and descrambled data and timing signals from module

U7 (and U12) at pins 2, 3, 5 and 6 are provided through

A3; CLB and BLB signals from LOOP TEST switch

pull-up resistors R14, R15, R20 and R23. Resistors R24

1A12S3; 4) 1HIBTR signal from AVOW switch 1A12S2;

through R27 perform a similar function for U12. Only

and 5) signals from DATA RATE SEL (MB) switch

two of the four switches in U7 are used. When LOOP

1A12S4.

TEST switch (S3) is in either the OFF (NORMAL) or

RADIO position, the input at P1-J and at U7-1 is logic 1

(1) Signals DATA and TMG from the

(via pull-up resistor R12). The DSCRM DATA signal

DGM are applied to level converter U4. Resistors R3,

(from module A5) at U7-3 is then connected to output

R4, R10 and R11 are impedance matching line

1Y (pin 4), and the DSCRM TIMING signal at U7-6 is

terminations. Bias voltages for U4 are applied through

connected to output 2Y (pin 7). When LOOP TEST

resistors R2, R6, R8 and R13. Capacitors C1 and C2

switch is in DGM position, the signal at U7-1 is logic 0

are for supply voltage bypass. The TTL level BFRD

and the signals at U7-2 (BFRD DATA) and U7-5 (BFRD

DATA AND BFRD TMG signal outputs of U4 are applied

TMG) are connected to the outputs at U7-4 and U7-7,

through inverter line buffers (U6E, U6D) to digital

respectively. The selected outputs at U7-4 and U7-7 are

randomizer module 1A12A3. Voltage levels for the logic

routed to the DGM

1 state are applied through resistors R5 and R9. The

outputs at U4-4 and -9 are also applied to multiplexer

U7.

Change 6 2-16.10