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TM 11-5820-695-35
from the remote site is detected in the receiver and the
the same.  At Digital data combiner 1A12, OW SEL
recovered data/orderwire signal is routed to 1A12
switch 1A1251 must be set to DGTL or ANLG position
through 1A13. In 1A12, the data and orderwire signals
according to the orderwire mode selected.
are separated, retimed, regenerated, and demultiplexed
(digital orderwire), then routed to the DGM and OCU.
(1)  In the transmit direction, when operating in
For analog orderwire, the AVOW signal is routed to
digital orderwire mode, the digital orderwire signals
1A13.
(DOW and DVOW) and the data signal are combined in
1A12 and the combined signal is adjusted to the level
(3)  The signals use in digital data combiner
required by the transmitter modulator circuits.  For
1A12 block diagram descriptions are listed below.
analog orderwire mode (AVOW), the orderwire signal is
Status and alarm signals have a not bar, (e.g., CLB, to
sent to orderwire assembly 1A13.
In lA13 it is
indicate that logic 0 is the active state and logic 1 is the
processed as described in paragraph 2-8.  In analog
inactive state). Thus, when LOOP TEST switch 1A12S3
orderwire mode, there are no digital orderwire signals to
is in the OFF or RADIO position, CLB is logic 1
combine with the data signal and the output from 1A12
(inactive).  When S3 is in the DGM position, CLB is
to the transmitter circuits consists of the data signal
logic 0 (active). FR FAIL is logic 0 normally and goes to
only. The data signal and the analog orderwire signal
logic 1 (fault) when the from radio data signal fails. For
are combined in module 1A4, as described in paragraph
the OW SEL switch (1A1251), signal AVOW/DVOW is
logic 1 for ANLG (which selects AVOW) and logic 0 for
DGTL (which selects DVOW).
(2)
In the receive direction, the radio signal
Mnemonic
Meaning
AVOW/DVOW
Signal from OW SEL switch 1A12S1
BFRD DATA
Buffered data signal from DGM
BFRD TMG
Timing signal for BFRD DATA signal
BLB
Signal from LOOP TEST switch 1A12S3
CDOW FAIL
Data status signal from 1A12A1
CLB
Signal from LOOP TEST switch 1A12S3
CLOCK
32 KHz clock for retimed data from radio CVDOW signal
CVDOW
Multiplexed DVOW and DOW signals
CVDOW RPLL FAIL
Status signal for 1A12A6
Change 6 2-8.4


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