Section IV. FIRST IF. STAGES, SECOND RECEIVER MIXER AND SECOND OSCILLATOR

Section IV. FIRST IF. STAGES, SECOND RECEIVER MIXER AND SECOND OSCILLATOR

25. First If. Amplifier V301

C311 couples the signal to the control grid

(fig. 8)

of V302 through parasitic-suppressor re-

sistor R307. Resistor R306 decouples the

a. On receive, first and second if. am-

if. signal from the avc source. The cathode

plifiers V301 and V302 amplify the 20.0-

bias for V302 is provided by resistors R323

to 29.9-mc first if. The amplified first if.

and R308. The dc voltage developed across

is heterodyned in V303 with the 17.0- to

R308 is applied to the S-METER circuit

26.0-mc output of second oscillator V305

through plug B of P301 to indicate the Input

(fig. 9) to produce the 3.0- to 3.9-mc if.

signal strength. Capacitors C322 and C323

b. The 20.0- to 29.9-mc if. signal from

ground the cathode for if. signals. Jack

first receiver mixer V104 (para 15) is

J302 is a test point for measuring avc

coupled from plug P303 through coupling

voltage on the grid of V302.

capacitor C301 to parallel-tuned circuit

b. Series resistors R309, R325, and R326

Z301. Coupling capacitor C303 couples the

form a voltage divider which provides

if. signal to parallel-tuned circuit Z302.

proper plate and screen voltages to V302.

Avc blocking capacitor C305 couples the if.

Resistor R309 and capacitors C324 and

signal to the control grid of first if. am-

C328 decouple if. signals from the +125-

plifier V301 through parasitic-suppressor

volt supply. Capacitor C347 grounds the

resistor R324. Inductors L316 and L317

screen of V302 for if. signal. A coupling

are harmonic suppressors. Jack J301 is a

network 2305, C314, Z306, and C316 cou-

test point for measuring avc voltage at the

ple the amplified if. signal from the plate

control grid of V301. Resistor R301 and

of V302 to the control grid of second re-

bypass capacitor C326 decouple the if. sig-

ceiver mixer V303.

nal from the avc bus. Resistor R302 pro-

vides cathode bias for V301 and bypass

27. Second Receiver Mixer V303

capacitor C319 grounds the cathode for if.

(fig. 8)

c. Series resistors R303, R304, and

R305 form a voltage divider which provides

a. The 17.0- to 26.0-mc signal produced

proper plate and screen voltages to V301.

by second oscillator V305 (para 28) is

Resistor R304 is connected to the +125-

coupled to the cathode of second receiver

volt supply through terminal K of plug

mixer V303 through coupling capacitor

P301, and R303 is grounded through term-

C325. The 17.0- to 26.0-mc signal is het-

inal M of plug P301 by tr relay K601 and

erodyned with the 20.0- to 29.9-mc if. sig-

contacts 2 and 13 (fig. 23). (On transmit,

nal from V302 to produce the 3.0- to 3.9-

relay contacts 2 and 13 of K601 open the

mc difference frequency. Jack J303 is a

ground return for R303 and raise the

test point for measuring the bias voltage

screen grid voltage to V301.) Resistor

developed on the grid of V303.

R304 and capacitor C321 decouple if. sig-

b. Plate voltage is applied to V303 from

nals from the +125-volt supply. Capacitor

the +125-volt dc supply tjrough plug P304.

C320 grounds if. signals at the screen grid

Inductor L312 is the plate load for V303.

of V301. Parallel-tuned circuit Z303 is the

Screen grid voltage is received from the

plate load for V301. Coupling capacitor

+125-volt dc source through voltage drop-

C308 couples the if. signal developed

ping resist or R312. Capacitor C318

across Z303 to parallel-tuned circuit Z304.

grounds the screen grid for rf signals. Re-

sistor R311 provides cathode bias for

26. Second If. Amplifier V302

C303. The 3.0-to 3.9-mc output of V303 is

(fig. 8)

applied to the 3.0- to 3.9-mc if. subunit

a. Second if. amplifier V302 provides

through harmonic trap L312 and plug P304.

additional amplification to the 20.0- to

Inductors L319 and

and capacitor

29.9-mc signal. Avc blocking capacitor

C339 form a harmonic suppressor network.