MEMORY LOAD LOGIC ( 1A3A2)

TM 11-5820-917-13

be loaded into the CRT memory ( 1A3A1) . The counter advances one position

every time new data is loaded into the CRT memory, typically once per second.

Another 9-bit counter, the moving cursor register (up /down counter U 40, U 41,

U 48, figure FO- 14/2) , provides the 9-bit address of the moving (blinking) cursor,

which may be changed by front panel pushbuttons. Six 9-bit fixed cursor regis-

ters ( figure FO- 14/4 and FO- 14/5) store the address of the moving cursor when

the STORE switch is actuated. U21 through U 38 provide storage for the six fixed

cursors. The status of a cursor is determined by the busy register, U23- 8,

U26-8, U29-8, U32-8, U35-8, U38-8, one flip flop per cursor.

The busy register shows whether the register is already being used to store a cur-

sor location or is available for a new location to be stored. Control for cursor

storage is provided by U 54 and U 55 (figure FO- 14/ 3). When a cursor is to be

stored, the RS flip-flop formed by U 54-3 and U54- 6 is set. This allows logic 1's to

be clocked into U 55. These logic l's activate CL1 (cursor load 1) to CL6 one at a

time until an unused register is found. Then the moving cursor address is clocked

into this register, the busy register is set, and a pulse is generated through CLF

to clear the RS flip-flop.

4-45. To erase any one cursor, the moving cursor must be positioned on top of

the cursor to be erased. To monitor this condition, the locations are checked

line by line during each vertical retrace of the CRT display by shift register U 8

(figure FO-14/3). When the ERASE switch is actuated, U8, U52, and U53 com-

pare the address of the moving cursor to those addresses stored in the six fixed

cursor registers. If any of these registers contain the same address as the

moving cursor address, one (or more) of the lines CE 1 through CE 6 goes low

erasing the address from the corresponding register and clearing the correspond-

ing busy register flag.

4-46. A 9-bit, 8-position multiplexer switch (U12-U20, figure FO-14/6) is used

to sequentially cycle between the 9-bit outputs of the moving cursor register

(U40, U41) , the six fixed cursor registers (figure FO-14/4 and FO-14/5), and

the spectrum analyzer load line counter (U50, U51) . During each raster vertical

retrace interval, U 12-U 20 is cycled through all eight of its positions by control

lines CSB2, CSC2, and CSD2. The 9-bit output of the switch is fed to the 9-bit

comparator on assembly 1A2A2 which compares the output of the raster vertical

line counter to the output of the 9-bit multiplexer. As the multiplexer cycles

through the addresses of the moving cursor (position O) , the six stored cursors

(positions 1-6) and the spectrum analyzer load line (position 7) , the comparator

on 1A2A2 yeilds a true output if the raster vertical line number equals the stored

address of one of the eight display lines. If this happens, an EQT pulse is gen-

erated by the comparator which indicates that the raster is now at the same

address location as one of the cursors. The EQT pulse is then used to initiate

one (or more) of three actions: (1) it causes a cursor line to be drawn on the

CRT by logic in 1A3A2, (2) it erases a cursor (1A2A1, figure FO-14/3), or (3)

it initiates a memory loading sequence (on 1A 3A 2) to load new spectrum data into

the main CRT memory. Description of the cursor to frequency converter circuit

(U43-U45, figure FO-14/2) is provided in paragraph 4-30.

4-47. MEMORY LOAD LOGIC ( 1A3A2) . This circuit provides the logic for

loading the CRT recirculating memory and outputs the video signal to the CRT.

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