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TM 11-5895-1141-34
(through the P/T switch) and at the same time the interlock bus is high the current into the (-) terminal of U1A is
predominant, forcing U1A output low. Now the junction of R43 and R44 is low as well as the U1 output. As a result the
current into the (-) terminal of U1C is reduced below that into the (+) terminal so U1C output goes high. Also, since R45 is
now returned to ground potential through the U1A output, U1B output goes low. These conditions result in Q8 turning on
and Q9 remains off. This is consistent with the initial conditions stated, the interlock bus high (transmitter not engaged by
any other operator) but S2 and the key switch both closed which should and does result in busy tone disabled and
transmitter status bus low. Note that K1 is energized which enables both transmitter keying and the transmitter audio
output line. The high interlock bus and the low transmitter status bus enables the microphone audio signal path to the
transmitter. If the interlock bus is low when S2 is closed and the P/T bus is grounded, U1A output is forced high. This in
turn forces more current into the (-) terminal of U1C through R42 so the U1C output drops low. With U1A output high, 1B
output is also forced high. These conditions result in Q8 off and Q9 on which corresponds to transmitter status bus high
and busy tone oscillator enabled. This is consistent with the initial conditions stated. At the volume control module the low
on Q9 collector will allow busy tone oscillator to turn on generating a tone that warns the operator the transmitter is already
engaged.  The low interlock bus and the high transmitter status bus keeps K1 de-energized and also blocks the
microphone audio. The logic of the interlock circuit is represented by an equivalent logic circuit shown in figure 2-9 where
the U1A,B,C amplifiers are shown as NOR gates and Q8 and Q9 are replaced by inverters. The bubble on one input to
U1B represents an inversion of logic state of any input passing that point. Lamp DS4 turns on when the transmitter is
keyed on by any operator. When either the interlock or transmitter channel status bus is low U1D output goes high
saturating Q6 and providing full lamp current for DS4.
f.
Volume Control Module Assembly. Refer to the schematic diagram of figure FO-10. This module is contained
within the audio unit enclosure. For this module, the actual component designations are the basic numbers shown on the
diagram, added to 1100. Thus, the module plug shown as P1 is actually P1101. For brevity of discussion, the basic
numbers will be used. Power for this module is delivered from the lamp brightener module assembly to pin 3 of P1 via the
filter choke and capacitor L101 and C101. Power is returned on pins P1-5 and P1-20. The volume control module
contains the following circuits: headset and loudspeaker summing amplifiers, regulated amplifier, headset driver amplifier,
and busy tone oscillator.
(1)  Headset Summing Amplifier. Refer to figure 2-10. The total of the received audio signal currents that are
routed by various selector modules to the headset amplifier bus which enters this module at P1-7 are
2-22


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