SWEEP SYNTHESIZER (P/N 5030-1001 Only)

TM 11-5820-918-13

4-18. The synthesizer module may be used without modification in either the receiver

or transmitter. For TCS-4B applications, the 2-30 MHz output is used directly to

drive the 5018 RF amplifier. For RCS-4B applications, the basic RF sweep is offset

200 kHz higher to produce a 42.2 -70.2 MHz receiver 1st L.O. from the microphage syn-

thesizer and a 2.2- 30.2 MHz receiver calibration signal from the synthesizer converter.

Selection of transmit or receive frequency formats is provided by a digital programming

line in the unit wiring harness connecting to the sweep synthesizer assembly.

4-19. The sweep synthesizer uses a single digital phase-lock loop (PLL) design em-

ploying a fractional phase computation technique that provides a phase-continuous (co-

herent) output sweep with 2 Hz frequency resolution. The fractional phase compu-

tation technique is a hybrid approach that combines the operation of a conventional

phase coherent, high frequency, low resolution, PLL synthesizer and a digitally con-

trolled, low frequency, high resolution, direct phase computation waveform generator.

The result is a PLL synthesizer capable of locking properly with a continuously chang-

ing programmed phase error within the loop. The programmed phase error capability

of this hybrid loop extends the frequency resolution of the basic PLL by almost five

decades.

4-20. The basic microphage synthesizer phase-lock loop (figure 4-2) consists of a vol-

tage controlled oscillator (VCO) having a frequency range of 42 to 70 MHz, a loop

amplifier/integrator, a phase detector, and a counter/divider/comparator string. This

basic synthesis loop is capable of synthesizing any frequency between 42 and 70 MHz

in 100 kHz steps as determined by the effective divide ratio in the divider between

the VCO and the phase detector. That is, for the VCO to operate at 45.1 MHz, the

divider must divide by 451 to achieve the required 100 kHz output for the phase de-

tector. (The phase detector reference is 100 kHz.) Another way of considering this

loop is to note that during the 10 microsecond period of the phase detector reference,

the VCO must advance exactly 451 cycles (zero crossings) if the loop is to lock prop-

erly. To synthesize 45.15 MHz with this loop would imply 451 1/2 cycles of phase

every 10 microseconds. By adding additional logic to the basic loop, the synthesizer

can operate properly by processing for the integer (451) and fractional (1/2) cycle

of phase information. For example, for the synthesizer to operate continuously at

42.123000 MHz, the phase (i.e., VCO zero crossings) must advance 421 whole cycles

plus 23/100 fractional cycles every 10 microseconds. A phase computer computes both

the exact whole number and fractional number of phase cycles of the programmed fre-

quency occurring in a 10 microsecond period. The result of this phase computation

is then added to the stored phase value from the previous 10 microsecond frame. For

example, assume a continuous frequency of 42.123 MHz, and a phase register initially

at zero. During the first 10 microsecond frame, the phase computer calculates 421.23

cycles of phase. For the second 10 microsecond frame, the VCO advances another

421.23 + 421.23 = 842.46 total cycles by the end of the second frame. Similarly, for

the third frame, the phase is advanced to 842.46 + 421.23 = 1263.69, and so on.

4-21. The synthesis loop operates by comparing and changing the VCO output phase

to equal that of the phase computer for both integer and fractional cycles. Integer

cycles (e.g., 421) of VCO phase are controlled by conventional phase-lock loop tech-

niques employing a high speed BCD counter and digital phase detector. The fractional

remainder of VCO phase (e.g., 0. 23) is handled by the residue generator. The res-

idue generator is digitally programmed waveform generator, controlled by the phase

computer, that corrects the output of the loop phase detector for the remaining frac-

tional cycle phase error occurring every 10 microseconds. It is this programmed, frac-

tional cycle, phase error correction capability that allows the loop to operate to a much

finer frequency resolution than can normally be expected from a conventional (integer

4-5