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Page Title: RECEIVE DATA SIGNAL PATH. Continued
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TM 11-5820-890-30-5 2-12. RECEIVE DATA SIGNAL PATH.  Continued The RADIO PTT-N line is held at logic 1 during receive mode. The data signal is recovered from the carrier by the RF section, which routes it to the switching module as FM DEMOD. See figure FO-5. A crossover detector senses the  presence  of  the  signal.  The  bit  sync/digital  squelch  network  synchronizes  the  local  clocking  with  the  data. When synchronized, the BS/TONE SQUELCH line is set to logic 1. PT DIGITAL CLK provides clocking for the data signals. It is a 16 kHz square wave, at logic 0/1 levels, that is generated by the switch control. RCV PT DATA and PT  DIGITAL  CLK  are  routed  to  the  audio  section  of  the  RT. The data and clocking signals are buffered and routed to the audio control module. Audio control processes and switches the signal thru to the audio/data l/O module. The signals are amplified to the correct levels and output to the  RT  AUD/DATA  connector  (J4).  DIGITAL  DATA  RCV  (DDR)  and  DIGITAL  DATA  CLK  OUT  (DDCO)  output  signal levels  are  5  V  for  logic  0  and  -5  V  for  logic  1.  Analog  data  signal  levels  are  0.77  Vrms  ±3  dB. When operating in FH mode, data received signals are routed through the ECCM module. The switching module sends  the  bit  synchronized  data  (BS  DATA)  to  the  ECCM  for  deinterleaving.  FH  DATA  is  returned  to  the  data receive  path. Receive  data  cipher  text  (RDCT)  is  routed  to  the  COMSEC  connector  from  the  switching  module  when  the  RT operates  in  cipher  text  mode.  The  COMSEC  device  decodes  the  signal  and  returns  the  data  receive  signal (AR/DDR) to the audio control module. The COMSEC device generates a clock signal for the data (AT/DDCO) and  routes  this  to  the  audio  control  module  also. Each  data  transmission  is  preceded  by  a  sync  preamble.  This  preamble  is  generated  by  the  data  rate  adapter section  of  the  ICOM  control  module,  It  provides  a  synchronization  source,  tells  the  RT  a  data  transmission  is being received, and whether the signal is plain or cipher text. During receive mode, the data rate adapter section monitors  the  RCV  DATA  output  from  the  audio  control  module.  When  the  preamble  is  detected,  the  NO  CODE DETECT  line  will  set  to  logic  0.  CODE  X/R  ENBL  is  at  logic  1  during  preamble  detection. When the DATA switch is set to AD2 or one of the other data rates, the audio control module sends the signals to the data rate adapter (RCV DATA and RCV CLK). The data and clock signals are converted to LO-SPD DATA and LO-SPD  CLK.  LO-SPD  DATA  SEL-N  at  logic  0  switches  these  LO-SPD  signals  back  into  their  proper  paths. The AD2 signal is tapped from the LO-SPD DATA line. It is shaped by an RC circuit into the necessary analog signal  by  the  audio/data  I/O  module. 2-13. TRANSMIT DATA SIGNAL PATH. The RT can process analog data and digital data. Analog data is input on J4 pin D (AT/DDCO). See figure FO-6. If the data rate is set to AD2, J4 pin F (ADMC/DDT) must be grounded for proper operation. The analog data signal will be converted to 16 kb/s digital data by the RT. If the data rate is set to AD1, the signal follows the audio path. Digital data is input on J4 pin F (ADMC/DDT). Pin E (DDMC) must be grounded. The RT provides a clock on J4 pin D  (DDCO)  and  the  digital  data  signal  must  be  synchronized  with  the  clock. For AD2, the analog data signal must be FSK modulated at 1200/2400 Hz. It is routed through the audio/data I/O module. An AGC amplifier and limiter adjust the level and the signal is output as LIMITED ANALOG DATA. The audio control module demodulates the FSK signal to convert it into a low speed digital signal. This signal is routed through the data rate adapter section where it is converted into a 16 kb/s digital data stream (XMT DATA). It is routed to the audio power supply where the signal is buffered and then routed through the switching module to the   exciter/power   amplifier. The digital data transmit (DDT) signal will be input as a ±5 V square wave, It is converted to logic 0/1 levels by the audio/data I/O module. The logic 0/1 level signal (DIGITAL DATA XMT) is routed to the audio control module. If it is anything other than 16 kb/s, it is routed to the data rate adapter section. It converts the data rate to 16 kb/s and returns the signal. The signal is routed to the audio power supply where it is buffered and sent to the switching module.  The  switching  module  routes  the  signal  to  the  exciter/power  amplifier. 2-16


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