TM 11-5820-882-23/TM 06827A-23/2
the output frequency of the vco with the 4 prescaler in
switch). The two bands are required to cover the 30 to
the vco module. The prescaler output is routed to the
80 MHz range of the radio set with varactor tuning.
mixer in the synthesizer module. The output of the mix-
c. The basic purpose of the frequency synthesizer is
er is the difference frequency of the prescaler input and
to generate the discrete channel frequencies with an ac-
the 10 MHz or 12.5 MHz reference oscillator.
curacy of 25 ppm. This is accomplished by phase lock-
ing a voltage controlled oscillator (VCO) to a standard
f. Because the capture range of the phase detector is
crystal controlled reference frequency. The reference
narrow (approximately 500 kHz at the vco frequency),
frequency of the synthesizer is 12.5 kHz crystal oscilla-
the vco must be swept over its frequency range to a fre-
tor by a factor of 800, or dividing the output of the 12.5
quency within this capture range. When this occurs, the
phase detector output control voltage (superimposed on
MHz crystal oscillator by a factor of 1000. The division
factor is determined by the position of the A switch. The
the sweep voltage) pulls the vco into phase-lock with the
reference frequency of the synthesizer.
reference divider ( K) consists of an injection locked
oscillator which divides by 4 (10 MHz) or 5 (12.5 MHz),
g. The sweep voltage is a sawtooth staircase
and a fixed divide ratio (200) digital counter. The 12.5
waveform consisting of additive coarse tune voltage
kHz output of the reference divider is routed to the
steps over a voltage range from 1.5 vdc to 13.0 vdc. The
phase comparator (detector).
ramp sweeps the vco over its frequency range by stepp-
ing up from 1.5 vdc to the coarse tune voltage required
d. To achieve phase locking, the output of the vco
to put the vco frequency within the capture range of the
(42 to 68 MHz) must be frequency translated and divid-
phase detector. Once phase lock is achieved, the ramp
ed douwn to 12.5 kHz for phase comparison with the 12.
stops and holds at that coarse tune voltage. The tune
5 kHz reference frequency. Because the vco must pro-
voltage output from the synthesizer is the phase detector
vide 520 discrete frequencies spaced 50 kHz apart, a
control voltage superimposed on the ramp coarse tune
variable frequency divider is required to divide each one
voltage. The level of the phase-locked tuning voltage is
of these discrete frequencies down to 12.5 kHz. The
proportional to the selected operating frequency, and
variable divider ( N) ratio is determined (programmed)
varies from 2.0 vdc to 11.0 vdc.
by setting the synthesizer switches to the code cor-
responding with the desired operating frequency. Once
h. The loop filter attenuates the 12.5 kHz reference
the N ratio is programmed, the vco can phase lock on-
frequency to minimize frequency modulation of the
ly at that frequency which translates down to 12.5 kHz.
i. The synthesizer also generates the battery saver
e. Because the maximum counting speed of the
cmos programmable divider is 5 MHz, the 42 to 68 MHz
timing waveform and the 150 Hz squelch tone wave-
range of the vco must be frequency translated down to
form, Both of these signals are derived from the crystal
less than 5 MHz. This is accomplished by first dividing
reference frequency with digital frequency dividers.