Phase and Amplitude Control Board 2A2 Detailed Functional Operation

TM 11-5820-873-34

coupler control, controls 2A1Q1 operation The gain

g. C3/C6 Control Assembly. Components 2A1Q6,

input establishes the reflected power threshold that

2A1Q7, 2A1U2 and their associative circuitry make up

causes 2A1Q1 conduction Transistor 2A1Q2 converts

the C3/C6 control Capacitor 2C3 is switched in and out

the 2A1Q1 output into an on/off output characteristic of

of the circuit in the following way. Each time the time

reflected power When 2A1Q2 conducts, it represents

delay runs out, 2A1U2C inverts the logic 0 from Time

reflected power above threshold With 2A1Q2 off,

Delay 2AlQ18 to logic 1. The logic 1 (2A1U2-8) then

reflected power Is below threshold and a positive

triggers 2A1Q6 to provide a ground at 2XA1-17 which

voltage is felt at the base of 2A1Q3 Transistor 2A1Q3

energizes bistable relay 2A5K2. Bistable relay 2A5K2 is

conducts when reflected power is below threshold and

the control for 2K3 which controls 2C3A-B Control of

its collector is at ground The 50 (-) output of board 2A1,

2C6 also utilizes a bistable relay, 2A5K1 It is controlled

at 2XA1-8, is taken from the collector of 2A1Q3 Also,

by 2A1U2A-B-D The L max signal, a logic 0, is produced

2A1Q3 drives 2A1Q4 Transistor 2A1Q4 and associated

when 2L4 reaches maximum inductance. This logic 0

components establish a short time delay The time delay

comes in on 2XA1-T to 2A1U2D and is inverted. The

prevents brief intervals of reflected power drop from

logic 1 at 2A1UD-11 then triggers 2A1Q7 to provide a

terminating a tuning cycle The 2A1Q4 output operates

ground at 2XA1-V. That ground toggles 2A5K1 into its

2A1Q5 to provide logic outputs characteristic of

opposite state. This action either switches 2C6 in or out

reflected power level A logic 1 from 2A1Q5 indicates

across 2L4, depending on its previous condition. If 2C6

reflected power below threshold The logic 1 is fed to

is switched across the 2L4, +28 VDC is also switched on

Tune FF 2A1U4C-9 to terminate the tune cycle Diode

to 2XA1-U. This +28 VDC is reduced to a logic 1 level

2AlCR1 and resistor 2A1R7 in the Reflected Power Amp

by voltage divider 2A1R19 and 2A1R20. The logic 1 is

cut it off during receive mode This prevents keying

then fed to 2A1U2B-5 and a logic 0 is then present at

spikes from causing the CPLR STATUS FAULT

2A1U2B-6. That logic 0 is inverted by 2A1U2D and

indicator to come on when unkeying.

again 2A1Q7 is triggered Bistable relay 2A5K1 is

toggled into its opposite state and 2C6 is either switched

in or out across 2L4. It should be noted that if 2L4

e. Time Delay.

The time delay consists of

reaches L min and 2K2 is not energized, 2A5K1 will not

2A1Q16, 2AlQ17, 2AlQ18 and their related components

be toggled. Also, if a tune cycle is initiated, 2A1U2A

Variable resistor 2A1R46 adjusts the length of the time

has a logic 0 output. At this time, if 2C6 is across 2L4, it

delay The normal time delay setting should be

will be removed.

approximately 40 seconds Time Delay operation is as

follows When a tune cycle is initiated, the collector of

2A1Q16 rises to near +VDC Capacitor 2A1C40 begins

Lamp Driver.

The three CPLR STATUS

charging thru 2A1R47 and the anode of 2A1Q17

indicators, on the antenna coupler control, are controlled

increases toward +5 VDC Transistor 2A1Q17 is a

by 2A1Q9, 2A1Q11 and/or 2A1Q12.

These lamp

programmable unifunction transistor that fires when the

drivers are turned on by logic signals at the appropriate

anode voltage reaches the voltage applied to the gate

times. The CPLR STATUS FAULT lamp driver is

Voltage divider 2A1R49 and 2AlR50 sets the gate

2A1Q12. It is triggered on anytime the Fault FF has a

voltage at approximately +5 VDC When 2A1Q17 fires,

logic 1 at 2A1U4A-3 Lamp driver 2A1Q11 lights the

the positive pulse triggers 2A1Q18 and 2A1Q18

CPLR STATUS READY indicator. This happens with a

collector produces a logic 0. The logic 0 resets the

logic 1 from the Tune FF at 2A1U4D11 CPLR STATUS

Tune FF thru 2A1CR21 and the Fault FF thru 2A1CR20.

is lit by 2A1Q9 with a logic 1 from Tune FF 2A1U3B-6.

This terminates the tune cycle and lights the CPLR

STATUS FAULT indicator Diode 2A1CR26 places a

2-15. Phase and Amplitude Control

logic 0 on the L max line to terminate the L force

Board 2A2 Detailed Functional Operation

function at the end of the time delay.

(Fig FO-7 and FO-34)

f. RF Detector. The RF Detector is comprised of

Board 2A2 processes inputs from Phase and Amplitude

2A1Q8 and its associated components. When RF Is

Detector 2A4 to provide drive signals for Servo Motor

sensed on the transmission line, a DC signal is present

Control 2A6. Thirteen functions are contained on 2A2.

at 2XA1-B This signal is coupled into the RF detector

These functions are: Phase Preamp, Phase Level

thru an RC network, 2A1R23 and 2A1C34 The RC

Changer, Phase Positive Logic Generator, C1 Home-

network allows 2A1Q8 to trigger on only when a

Flip-Flop, C1 Drive Inhibit, Phase Servo Preamp,

constant DC level is present Erratic levels and spikes

Amplitude Preamp, Amplitude Level Changer, L4 Home

are shunted to ground through 2A1C34. This prevents

Flip-Flop, L4 Force Flip-Flop, L4 Drive Inhibit, Amplitude

noise from turning the antenna tuner off when the

Servo Preamp and Phase/Amplitude Brake.

transmitter is first keyed on when 2A1Q8 triggers on, a

logic 0 is generated at the collector and inverted by

2A1U3. The logic 1 from 2A1U3-3 is fed to the Fault FF

(2A1U4C-10) and the 50 ohm FF (2A1U6B-5).

2-18